ML/AI in Semiconductor Packaging and Electronics Manufacturing
Aug 30, 2021 · By Dr. Dongkai Shangguan · 3D In-Depth, Manufacturing
Design View all
Let’s Start the ESD Alliance – 3D InCites Conversation!
This post kicks off what I expect to be a regular series of blogs that will help tie the system design community to manufacturing or, more specifically, your community tackling 3D integration. I accepted Francoise’s invitation to become a 3D InCites blogger because the ESD Alliance, where I serve as...
EDPS 2020: An Inside Look at the Manufacturing-centric Presentations
Like many other industry conferences, the Electronic Design Process Symposium (EDPS 2020) had to go virtual. Not only did it keep our audience safe but allowed us to attract almost 200 registrants worldwide. Thanks to sponsorships from – ANSYS, Cadence, CEDA, Intel, Mentor – A Siemens Business, and Synopsys –...
Devices View all
How AiP Technology Helps Enable 5G and More
For 5G smartphones and other millimeter-wave (mmWave) applications, antenna integration, either through antenna-in-package (AiP) or antenna-on-package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit, and function for these applications and can include...
System-on-Chip Disintegration is Underway
We have known for some time that with scaling coming to an end the industry would need to find another way to continue moving forward. One of the options is known as SoC disintegration, which is when a system-on-chip (SoC) is disintegrated into its functional parts and then connect these...
Latest Posts
Hybrid Bonding Bridges the Technology Gap
A Technology Chasm Until recently, the world of IC fabrication was neatly divided into the distinct stages of front-end and...
Will An Adhesion Promoter Prevent Delamination in Power Semiconductor Packages?
Power semiconductor packages are used in high temperature, high voltage environments. With the increase of electric vehicles (EVs) and hybrid...
Die-to-Wafer Bonding Steps into the Spotlight on a Heterogeneous Integration Stage
The semiconductor industry is currently undergoing the most radical change in its history. Many new applications such as artificial intelligence...
Novel Approaches to Wafer Handling
Economics are forcing semiconductor manufacturers away from traditional 3D through silicon via (TSV) packaging integration. The future of advanced packaging...
Glass-based Solutions for Packaging are Here
A number of research articles have been published over the past several years showing the advantages glass-based solutions can bring...
Thoughts on the Post-COVID-19 Semiconductor Supercycle
As we head into Q2 of 2021, it seems that the world is finally approaching “normalcy.” But I don’t believe...
Fine-Pitch 3D Stacked Technologies for High-performance Heterogeneous Integration and Chiplet-based Architectures
3DIC Integration using 3D stacked technologies in its true definition has a long history.1 Richard P. Feynman expressed this vision...
The Importance of Product Burn-In Test
Introduction Product burn-in (BI) is an indispensable step in the production test flow to ensure good quality and a properly...
What Does Panel-level Packaging Mean for Seed Layer Deposition?
Seed layer deposition is one of the most critical process steps in manufacturing vertical and horizontal interconnects. At the panel...
Increasing the Conductive Density of Power Packaging
March 3, 2021 – Wide bandgap (WBG) semiconductor technologies have created new challenges and opportunities for power packages. Developments such...
3D: The El Dorado of Heterogeneous Integration
From the cloud to edge computing, the quest for ever-greater power efficiency remains researchers’ top priority. From high-end niche to...
IFTLE 476: 2020 3D Test Workshop – IMEC Co-Packaged Optics & Intel Foveros Testing
November 2020 saw the 7th IEEE International Workshop on Testing 3D, Chiplet-Based, and Stacked ICs (which IFTLE has been calling...
IFTLE 475: EPTC 2020: IME on Hybrid Bonding Challenges; Latest on Intel
IME – Hybrid Bonding Studies Singapore’s Institute of Microelectronics – IME / AStar – was certainly the most prolific presenter...
RF Technology in a Complete Glass Package
In order to remain competitive in the Internet-of-Things (IoT) environment, medium-sized industrial and process measurement technology companies must increasingly integrate...
Meeting the Challenges of 5G RF Production Test Services
Implementation of the 5G radio frequency (RF) standard is increasing rapidly [1]. Over the past four to six quarters, there...
CEA-Leti/Intel Collaboration brings 3D Powerhouses to the Advanced 3D Packaging Table
CEA-Leti and Intel recently announced a new collaboration effort on advanced 3D packaging technologies for processors to advance chip design....
Process Control and Inspection for High-Value Advanced Packages: It’s Complicated
In September of 2018, I spoke with KLA’s Stephen Hiebert and Pieter Vandewalle about the changing advanced packaging landscape, and...
Plasma Treatment During Fan-Out Packaging Maximizes Performance and Optimizes Costs
In recent years, there has been an increased focus on fan-out wafer-level packaging (FOWLP) due to the smaller packaging size...
Why We Need to Address Known Good Die (KDG) Holistically
If you love, like me, to work on the bleeding edge of technology, you will find that your personal success...