The expected increase of the power device market, with a compound annual growth rate (CAGR) of more than 10% — and more particularly insulated-gate bipolar transistor (IGBT) products for automotive and other applications — is pushing the semiconductor industry to adopt specific process solutions. The maturity of IGBT market, boosted by booming demand for electrified vehicles (EV) and hybrid el... »
The importance of surface preparation and wafer cleans during semiconductor device manufacturing is migrating from front-end wafer processing to back-end wafer level packaging processes. To get a clearer picture of how this impacts semiconductor equipment and materials suppliers, 3DInCites spoke with Anil Vijayendran, vice president of marketing at Veeco Instruments, Precision Surface Processing D... »
At this year’s International Wafer-level Packaging Conference, almost 1000 semiconductor experts from all parts of the supply chain gathered at the DoubleTree Hotel in San Jose from October 23 to 25. Among them were also several electronic design automation (EDA) experts who discussed how to streamline die-package-board co-design. They explained how EDA tools enable higher performance per Watt a... »
It’s almost ironic. As CMOS scaling (aka: Moore’s Law) has slowed due to the increased complexity and cost of achieving smaller nodes, the focus has shifted to advanced packaging and heterogeneous integration to meet demands for microelectronics devices targeting the internet of things (IoT) market. These devices perform a variety of functions (sensing, processing, remembering, transmitting) i... »
For the second consecutive year, SEMI Europe is co-locating its MEMS and Sensors/Imaging and Sensors Summits in Grenoble, France, in the heart of the Rhone-Alpes. Rather than Minatec Campus, where the event was held last year, both summits will take place at The World Trade Center Grenoble. After last year’s successful and information-packed event, I’m looking forward to attending this year’... »
One topic that has been under hot debate in the semiconductor advanced packaging sector for the past few years is fan-out panel-level packaging (FOPLP). In theory, the concept of taking fan-out from a 300-mm reconstituted wafer to a large panel format as a way to lower costs seems simple, and even the logical step. It’s not. Skeptics, many burned by the same low-cost advantage argument for inv... »
On Monday, April 16, 2018, SEMI, the industry association representing the global electronics manufacturing supply chain, and the Electronic System Design (ESD) Alliance, representing the design community, announced a strategic partnership. On Tuesday I had a very informative conference call with Bettina Weiss, VP Business Development at SEMI and Bob Smith, Executive Director, the ESD Alliance to ... »
Did you get your ECTC Advanced Program and Registration in the mail yet? Mine arrived yesterday, and I was pleased to see that this year’s Electronics Components and Technologies Conference (ECTC 2018), which takes place May 29-June 1, will be all about the new technology darlings driving development in heterogeneous integration: artificial intelligence, the human-machine interface, wearables, B... »
As it has for the past 14 years, the global microelectronics industry gathered at Wekopa Resort and Conference Center in Fountain Hills, AZ, March 6-8, 2018, for the 2018 IMAPS Device Packaging Conference (DPC) to share knowledge, discuss strategies for growth, learn about the latest heterogeneous integration from fan-out wafer level packaging (FOWLP) to 3D ICs. We also managed to get in some golf... »
March 7, 2018, the day of the 2018 3D InCites Awards Ceremony, dawned chillier than normal for this time of year in Fountain Hills, AZ. As they enjoyed their breakfast on the terrace outside the conference center, attendees of the 14th Annual iMAPS Device Packaging Conference (iMAPS DPC), may have noticed an artist hard at work creating an original mural that would later provide a backdrop to comm... »
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