Anyone who’s anyone with a hand in the evolution of wafer-level packaging will be in attendance or exhibiting at the 16th Annual International Wafer-Level Packaging Conference (IWLPC) and Tabletop Exhibition next week. 3D InCites will be there and we’re excited to engage and learn from the industry’s most respected authorities addressing all aspects of wafer-level, 3D device packagin... »
Most of today’s blockbuster MEMS products—from pressure sensors and resonators to accelerometers and microphones—originated from academic research, a trend that Alissa M. Fitzgerald, Founder & Managing Member, A.M. Fitzgerald & Associates, expects to continue. While many of these potentially game-changing new technologies will require many more years of intensive development and up t... »
The 52nd International Symposium on Microelectronics, organized by the International Microelectronics Assembly and Packaging Society (IMAPS) starts next week. Key package platforms will include system-in-package (SiP), system in module (SiM). chip-package interaction (CPI), wafer level/panel Level, 2.5D/3D/flip chip/optical, as well as high reliablity/performance, and advanced process/materials. I... »
Earlier this summer, 175 system-in-package (SiP) experts from all over the world met at the Marriott Hotel in Monterey’s Old Town at the IMAPS Advanced SiPs Conference. This conference focused exclusively on innovative SiP technology developments and trends, demonstrating that a significant part of the value creation is moving from the silicon to the package. Nozad Karim, VP: SiP/System Integrat... »
The expected increase of the power device market, with a compound annual growth rate (CAGR) of more than 10% — and more particularly insulated-gate bipolar transistor (IGBT) products for automotive and other applications — is pushing the semiconductor industry to adopt specific process solutions. The maturity of IGBT market, boosted by booming demand for electrified vehicles (EV) and hybrid el... »
The importance of surface preparation and wafer cleans during semiconductor device manufacturing is migrating from front-end wafer processing to back-end wafer level packaging processes. To get a clearer picture of how this impacts semiconductor equipment and materials suppliers, 3DInCites spoke with Anil Vijayendran, vice president of marketing at Veeco Instruments, Precision Surface Processing D... »
At this year’s International Wafer-level Packaging Conference, almost 1000 semiconductor experts from all parts of the supply chain gathered at the DoubleTree Hotel in San Jose from October 23 to 25. Among them were also several electronic design automation (EDA) experts who discussed how to streamline die-package-board co-design. They explained how EDA tools enable higher performance per Watt a... »
It’s almost ironic. As CMOS scaling (aka: Moore’s Law) has slowed due to the increased complexity and cost of achieving smaller nodes, the focus has shifted to advanced packaging and heterogeneous integration to meet demands for microelectronics devices targeting the internet of things (IoT) market. These devices perform a variety of functions (sensing, processing, remembering, transmitting) i... »
For the second consecutive year, SEMI Europe is co-locating its MEMS and Sensors/Imaging and Sensors Summits in Grenoble, France, in the heart of the Rhone-Alpes. Rather than Minatec Campus, where the event was held last year, both summits will take place at The World Trade Center Grenoble. After last year’s successful and information-packed event, I’m looking forward to attending this year’... »
One topic that has been under hot debate in the semiconductor advanced packaging sector for the past few years is fan-out panel-level packaging (FOPLP). In theory, the concept of taking fan-out from a 300-mm reconstituted wafer to a large panel format as a way to lower costs seems simple, and even the logical step. It’s not. Skeptics, many burned by the same low-cost advantage argument for inv... »
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