Warpage in Fan-Out Wafer-Level Packaging: Challenges and Research Directions at Arizona State University
Sep 08, 2026 · By Pallavi Jithendrriyan · 3D In-Depth, R&D and Collaboration
Design View all
A Legacy of Innovation: Celebrating 50 Years of VIEW Micro Metrology
VIEW Engineering: The Origins of Automated Optical Metrology In the 1970s, rapid advances in manufacturing created a growing need for automated optical measurement. CNC machining dramatically increased production speeds, while Statistical Process Control (SPC) required accurate, repeatable measurement data to maintain quality. At the same time, shrinking component sizes and...
Siemens advances self-verifying agentic AI workflows for semiconductor and PCB design
Combines Siemens’ EDA expertise and software with NVIDIA AI infrastructure and software to improve result quality, time-to-results, tool-calling reliability and token efficiency for long-running engineering workloads Enables agentic AI workflows that help engineers improve productivity and design quality across the electronic design automation (EDA) lifecycle Delivers more predictable, trusted outcomes...
Devices View all
How Implantable Brain-Computer Interfaces Are Pushing the Boundaries of Precision Die Bonding
A patient who can no longer speak generates text directly from neural activity. A patient with paralysis controls a cursor using thought alone. Behind demonstrations like these is a difficult engineering problem: how do you assemble electronics delicate enough to interact with the human brain, while keeping them stable inside...
Navy’s Directed Energy Systems Integration Lab to Train Sailors on Laser Weapons
By Thomas McMahon Naval Surface Warfare Center, Port Hueneme Division, CA Sailors can now get certified in operating and maintaining the fleet’s most prevalent directed energy system through a new training program at Naval Surface Warfare Center, Port Hueneme Division (NSWC PHD)’s Directed Energy Systems Integration Laboratory (DESIL), with the first...
Latest Posts - Page 3
Engineering Copper Grain Structure for High-Yield Hybrid Bonding in 3D Packaging
By Abdelhamid El-Sawy, Ph.D., Senior R&D Scientist and Bud Troche, Senior Director of Wafer Level Packaging, MacDermid Alpha Electronics Solutions...
A Comprehensive Approach to 3D IC Physical Verification: Tackling DRC, LVS and Beyond
As the industry pushes toward ever-greater levels of semiconductor performance, integration and efficiency, the promise of 3D integrated circuits (3D...
The Telecom Network Semiconductor Trifecta
Telecommunication networks are undergoing a rapid transformation. With 5G rollouts, edge computing, and a surge in IoT devices, the pressure...
Revolutionizing Semiconductor Quality: The Dynamic Planar CT Advantage
X-Ray inspection has become an essential component in semiconductor manufacturing, with 3D imaging emerging as a critical tool for ensuring...
Copper Dual Damascene for Wafer-Level Packaging: Enabling Reliable, High-Density Interconnects
Overcoming yield loss, reliability risks, and scaling limits in advanced packaging with high-aspect-ratio copper interconnects. As device architectures shrink, delivering...
An Inside-out-view: Data Centers
The convergence and synergy of performance and sustainability required to power the next generation of AI data centers The surging...
Managing Security and Access of Semiconductor Manufacturing’s Remote Connectivity
In the complex world of semiconductor manufacturing, equipment uptime is critical to productivity. Modern industrial operations are no longer limited...
Meeting the Cleaning Challenges of High-density 3D Heterogeneous Integration Applications
Today’s rapid growth in 3D heterogeneous integration (3D HI) is being driven by a plethora of high-performance computing applications driving...
Novel Semi-additive Process Streamlines RDL to Address Industry Roadmaps and Reduces Cost
The record attendance at ECTC a month ago in Dallas was just the latest indicator of the explosion of interest...
Yield and Cost Analysis of a Face-to-Back Chip-on-Wafer 3D Package
One form of advanced packaging is 3D stacking, in which two (or more) chips are stacked together. This differs from...
Revealing the Invisible: Optimized nano-CT Case Studies in Advanced Packaging
By Till Dreier and Julius Hållstedt, Excillum Complex architectures with intricate interconnects, stacked dies, and buried features – the recent...
Chiplets: Optimized Device Integration, Performance, and Time-to-Market
In the rapidly evolving microelectronics landscape, demands for higher performance, reduced size, and faster development cycles are driving the industry...
Ensuring Precision Calls For Certified Quality Logistics for the Semiconductor Industry
Editor’s note: This article originally appeared on Digitimes. In a world where semiconductors are the foundation of modern technology, powering...
The Next Frontier—AI for Semiconductor Test
By Ming Zhang, Ph.D., Vice President of Fabless Solutions While AI has made significant inroads in semiconductor design and manufacturing,...
An Integrated Cooling Solution for Hot Chips
Meeting the Thermal Challenge of High-Performance Compute ICs The semiconductor industry is undergoing a major transformation, driven by the demand...
Is Managing Alpha Particle Emissions Key to Mitigating Soft Errors in Advanced Packages?
Challenges in the Era of Semiconductor Miniaturization As process nodes continue to shrink, moving into the single-digit nanometer era, the...
Innovative High-density Adaptive Redistribution Technology for HIgh I/O Embedded Devices
By Lars Böttcher, Ruben Kahle, Claudia Landstorfer, Dionysios Manessis and Andreas Ostmann, Fraunhofer IZM To meet the requirements of high-density...
Foundry 2.0 – the New Path Forward for Moore’s Law
NHanced Semiconductor president Robert Patti’s presentation at the recent SEMIEXPO Heartland in Indianapolis, IN described the critical role of advanced...
The Evolution of Inspection and Metrology in the AI Era
By Bastian Troeger, Director Product Marketing & Sales Support; Eyal Segev, Director of Marketing As artificial intelligence continues to push...