UCLA Samueli School of Engineering launches $125 million semiconductor hub with top industry leaders
May 29, 2026 · By Applied Materials · 3D In-Depth, Manufacturing
Design View all
SWAP Hub earns DoW Year 2 Award Investment from NSTXL
The Microelectronics Commons NSTXL (National Security Technology Accelerator) has announced the DoW Year 2 awards, with more than $200M invested across 26 projects nationwide and the Southwest Advanced Prototyping (SWAP) Hub earning continued support for multiple high-impact efforts already advancing U.S. microelectronics innovation. These awards recognize real progress and growing...
Engineering Copper Grain Structure for High-Yield Hybrid Bonding in 3D Packaging
Why copper grain size matters for hybrid bonding and how to control it for HBM and chiplets. Read the article here. Abstract Hybrid bonding is reshaping advanced packaging by enabling ultra-fine pitch copper-to-copper interconnects, essential for high-bandwidth memory (HBM), chiplet integration, and 3D heterogeneous systems. While alignment precision, oxide control,...
Devices View all
Navy’s Directed Energy Systems Integration Lab to Train Sailors on Laser Weapons
By Thomas McMahon Naval Surface Warfare Center, Port Hueneme Division, CA Sailors can now get certified in operating and maintaining the fleet’s most prevalent directed energy system through a new training program at Naval Surface Warfare Center, Port Hueneme Division (NSWC PHD)’s Directed Energy Systems Integration Laboratory (DESIL), with the first...
How AiP Technology Helps Enable 5G and More
For 5G smartphones and other millimeter-wave (mmWave) applications, antenna integration, either through antenna-in-package (AiP) or antenna-on-package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit, and function for these applications and can include...
Latest Posts - Page 3
The Role of Chiplets in Redefining Semiconductor Design
Chiplets are transforming the semiconductor landscape. Rather than relying on larger, all-in-one designs, chiplets offer a modular approach to chip...
Multi-Tier Die Stacking Enables Efficient Manufacturing
Achieve higher integration density with collective die-to-wafer bonding Advanced packaging is currently facing a critical challenge to increase manufacturing efficiency...
Diving Deep into TSV Cleaning and Electroplating Processes For Heterogeneous Integration
By Jim Straus and Sally-Ann Henry, ACM Research While heterogeneous integration of multiple components and 2.5D/3D packaging techniques pair perfectly...
Expanding the Chiplet Market: Processing Any Wafer from Any Foundry
In response to the rising costs of advanced nodes and the slowdown of Moore’s Law, major vendors – AMD, Intel,...
Chiplet Test: Piecing Together the Next Generation of Chips (Part 2)
Testing the limits: standardization and optimization of chiplet test protocols Chiplets often come from different sources, making electrical testing challenging....
Chiplet Interconnect Technology: Piecing Together the Next Generation of Chips
Bridging the gap: innovations in chiplet interconnect technology Chiplet interconnects begin with small chips – or chiplets – with a...
Novel Surface Metrology Techniques for Hybrid Bonding
Executive Summary: Innovative, High Throughput Surface Metrology Hybrid bonding is enabling the next generation of advanced packaging in the semiconductor...
Thermal Simulation of a Packaged GaN MMIC
StratEdge has been designing and manufacturing packages for high-power, high-frequency compound semiconductors since the early 1990s, with much attention focused...
Five Workflows for Tackling Heterogeneous Integration of Chiplets for 2.5D/3D
Keeping pace with Moore’s law continues to be challenging and is driving the adoption of innovative packaging technologies that support...
Solving the AI Puzzle
An AI package is like a puzzle made up of individual pieces of different sizes and shapes, each one essential...
Balancing Precision and Throughput in 3D Structures with Advanced Packaging and Motion Control
The relentless drive in the semiconductor industry to consistently deliver improved performance and power efficiency has traditionally led to increasingly...
Rapid Development and Optimization of Thermal Management Solutions for Advanced Semiconductor Packaging
As the power density increases for semiconductor devices, thermal management is becoming an ever more critical challenge for reliability and...
The Year in Semiconductor Device Test
Is semiconductor device test non-value added? Certainly, some aspects are unchanging. Test is one of the three means to guarantee...When Plasma Matters: Three Reasons to Choose Plasma
Every metal layer on a wafer, from M1 at the front end to redistribution for wafer-level packaging (WLP), requires patterning....
Flux-less TCB for Fine-Pitch Applications and Its Extension to Cu-Cu TCB
Modern-day applications such as cloud computing, high-performance computing, artificial intelligence (AI), data centers, and future 6G systems are driving the...
How is X-ray Inspection Used in Semiconductor Manufacturing?
Technology is Key With the ever-present pressure to produce more efficient devices with more power, the sizes of the structures...
Saving The World with a Global Parts Platform
Legacy semiconductor manufacturing equipment and parts have a big role to play in helping the industry achieve its growth goals...
Thermal Test Chips (TTCs) for Advanced Semiconductor Packaging
Thermal management is becoming an ever more critical challenge for semiconductor devices, as the functional density and power density increase...
The Age of Hybrid Bonding: Where We Are and Where We’re Going
For decades, Moore’s Law has been a way to measure performance gains in the semiconductor industry, but the ability to...