Manufacturing

Convergence on the “Big Five”: Focus on WLCSP

Convergence on the “Big Five”: Focus on WLCSP

Part two of a five-part series. How did we determine which technologies are “the Big Five,” for semiconductor packaging? Essentially, we identified the five key platforms that we believe will be leveraged across a multitude of applications and markets now and in the future. The selected platforms are low-cost flip chip, wafer-level chip scale packaging (WLCSP), micro-electromechanical systems... »

TSV Technology Trends and Fabrication Details: A Short Course

TSV Technology Trends and Fabrication Details: A Short Course

3D/TSV technology has been the subject of intense development over the last 10-15 years. During this time, many process advancements were made and several basic questions were answered regarding when and how TSVs would be integrated. After tremendous progress on the technology side, much of the current focus is on 3D product launches and remaining commercialization issues, primarily cost reduction... »

Akrion Systems Intensifies Focus on 3D TSV Advanced Packaging

Akrion Systems Intensifies Focus on 3D TSV Advanced Packaging

Allentown, Pa., January 29, 2015 – Akrion Systems was well represented exhibiting at the 2015 European 3D TSV Summit earlier this month, as the company intensifies its focus on 3D TSV Advanced Packaging.  The company displayed and discussed its unique hardware and process technologies that reduce the cost of critical processes in advanced packaging. Process applications include advancemen... »

Executive Viewpoint: Executing a 3D Supply Chain eSilicon Style

Executive Viewpoint: Executing a 3D Supply Chain eSilicon Style

While the traditional foundry/OSAT supply chain has worked for fabless semiconductor manufactures engaging in the manufacture, package, and test of 2D architectures, it’s well understood that a 3D supply chain requires something different. 3D architectures bring new issues to the table such as yield management, sourcing from different suppliers, who tests what, who owns what, how do you make s... »

Kulicke & Soffa Stack the Dice for 2.5D and 3D IC Assembly

Kulicke & Soffa Stack the Dice for 2.5D and 3D IC Assembly

It’s been a long time coming, but Kulicke & Soffa has seen the writing on the wall, and it reads: “2.5D and 3D IC assembly is a hot market.” Why else would the wire-bond giant invest in developing a thermocompression chip-to-substrate (C2S) bonder for high-volume 2.5D and 3D IC die stacking processes? The company first dipped its toes in the die bonding market when it acquired Alphas... »

Setting the Record Straight On Applied Materials’ PVD Tool for 3D TSVs

Setting the Record Straight On Applied Materials’ PVD Tool for 3D TSVs

Nothing makes me click a link faster than a title like “3D Chip Stack Tool Sends TSV Into High-Volume”, because who in this industry isn’t waiting for that precise moment when through silicon vias (TSVs) go into high volume manufacturing? Unfortunately, the EE Times story behind that provocative title was a little less than accurate, because as we all know, one tool introduction isn’t goin... »

2013 ITRS Roadmap Calls for 3D Power Scaling; Monolithic 3D Gains Traction

2013 ITRS Roadmap Calls for 3D Power Scaling; Monolithic 3D Gains Traction

At the beginning of April, the Semiconductor Industry Association released the 2013 International Roadmap for Semiconductors (ITRS), which has traditionally served as a guide for “assessing and improving the future of semiconductor technology,” according to Brian Toohey, president and CEO, Semiconductor Industry Association. Sponsored by five regions of the world including Europe, Japan, Korea... »

ASE and Inotera Memories to Offer Novel 2.5D Manufacturing Solutions

ASE and Inotera Memories to Offer Novel 2.5D Manufacturing Solutions

Last week, ASE and Inotera Memories announced they had entered into a joint development project (JDP) intended to both strengthen ASE’s system-in-package (SiP) capabilities and expand Inotera’s foundry services beyond its core competency of memory manufacturing to silicon interposers. The goal is to provide novel 2.5D manufacturing solutions. Prior to the companies’ official announcement, ru... »

SUSS MicroTec Launches Mask Aligner MA200 Gen3

SUSS MicroTec Launches Mask Aligner MA200 Gen3

Garching, April 2, 2014 – SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, has launched the new Mask Aligner MA200 Gen3 today. The tool is designed for high-volume manufacturing and can be used for exposing wafers with a diameter of up to 200mm. This latest generation tool is a further development of the very successful MA200... »

Latest Developments in Cleans for TSVs and Cu Bumps

Latest Developments in Cleans for TSVs and Cu Bumps

At IMAPS DPC 2014, which took place March 11-13, 2014, in Fountain Hills, AZ, there were several presentations focused on new developments in cleans for TSVs and Cu bumps for 2.5D and 3D IC processes. Cleans has become increasingly important as bump pitches are reduced and TSVs have higher aspect ratios. It’s not just about being clean enough, but also about surface preparation for the next proc... »

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