3D In Context

About Herb Reiter

After more than 20 years in technical and business roles at semiconductor and EDA companies, Herb Reiter founded eda2asic Consulting, Inc. in 2002 to focus on increasing the cooperation between EDA suppliers and ASIC vendors. In this role Herb introduced innovative IC design tools to the major semiconductor vendors worldwide. In 2008 he expanded his scope into Multi-die ICs. As chair of the GSA’s 3D-IC Working Group (2008-2011) and as SEMATECH business development consultant (2012 + ‘13), he broadened his horizon to include interposers and 3D-ICs technology, semiconductor materials as well as manufacturing, metrology and test equipment. In 2014 + ’15 Herb consulted with Si2, to encourage development and standardization of data exchange formats for Interposer and 3D-IC design flows. Since early 2016 he is consulting with the newly formed Electronic System Design Alliance (formerly EDAC), to accelerate market acceptance of Multi-die ICs, the essential building blocks for the emerging System Scaling methodology.
Herb attended 40+ Continuing Education courses at Stanford University, earned an MBA at San Jose State University and Master Degrees in Business and Electrical Engineering at the University and the Technical College in Linz/Austria, respectively. He can be reached at herb@eda2asic.com

Here are my most recent posts

Sir Walter Raleigh towered above the 50th IMAPS Symposium

Sir Walter Raleigh towered above the 50th IMAPS Symposium

Almost 500 years ago Walter Raleigh was born in England, rose rapidly in the favor of Queen Elizabeth I and was knighted in 1585. In 1587 he initiated the founding of Raleigh. Last week he welcomed – appropriately dressed – about one thousand semiconductor experts to the 50th International Symposium on Microelectronics at the Raleigh, NC, Convention Center (Figure 1). If you look closer at thi... »

EDPS 2017: NOT the usual Electronic DESIGN Process Symposium

EDPS 2017: NOT the usual Electronic DESIGN Process Symposium

When planning the 24th EDPS, the organizing committee, chaired by Shishpal Rawat, former Intel executive, took a number of bold steps EDPS was traditionally held in the spring. We moved EDPS to the fall because that’s a time when more new IC projects are being planned. After many years of holding it in Monterey, we moved EDPS to Milpitas to make it more easily accessible for Silicon Valley folks... »

Image Courtesy of TSMC Ltd.

TSMC’s OIP 2017 Symposium Shows The Awesome Power of an Ecosystem

Last week, September 13 to be exact, TSMC held its Open Innovation Forum (OIP 2017) Symposium at the Santa Clara Convention Center. Before getting into product and market details, allow me to share some of my general impression of this, as usual, very well-organized event. After several decades of experience with alliance management and ecosystem building, I see TSMC as the master of these discipl... »

IMAPS 2017 SiP Conference Takes on Sonoma

IMAPS 2017 SiP Conference Takes on Sonoma

California’s Wine Country attracts visitors from all over the world. They can enjoy the scenic countryside, historic places, golf courses, tennis courts, gambling and of course great wine and excellent food. How well can a highly technical conference compete with all these “distractions”? Please read about the sessions I attended and judge for yourself! The Inaugural Conference and Exhibitio... »

Take-Aways from Test Vision 20/20 Workshop and SEMICON West Advanced Packaging Sessions

Take-Aways from Test Vision 20/20 Workshop and SEMICON West Advanced Packaging Sessions

I am convinced that increasing device complexity, higher quality requirements (e.g. automotive and medical), as well as the need for faster production ramp-ups, will force our industry to pay even more attention to design-in quality, expand self-test, even add redundancy to control logic and interconnects. In addition, wafer-probe and final test need to be expanded. Therefore, attending the Test V... »

Mission Impossible? Not for SEMI!

Mission Impossible? Not for SEMI!

San Francisco’s Moscone Center (above), the traditional home of SEMICON West trade shows, is undergoing major reconstruction work. Looking at this picture of the South Hall you may ask yourself: “Can anybody organize a large trade show here and make it a big success?” My answer is: “YES, the SEMI team can! They did exactly this in July for SEMICON West 2017!” With some very creative spac... »

Tech Session Highlights from ECTC 2017

Tech Session Highlights from ECTC 2017

Françoise promised in her recent blog that my ECTC blog would follow shortly. Finally, after attending DAC in Austin as well as the iMAPS’ SiP Conference in California’s Wine Country and shortly before attending Semicon West in San Francisco, I found some time to report what I saw and learned at ECTC 2017 in Orlando. ECTC offered six parallel tracks for the about 1500 attendees. I could of co... »

New Design Flow and OSAT Alliance Program Jump-Start High-density Advanced Packaging

New Design Flow and OSAT Alliance Program Jump-Start High-density Advanced Packaging

Editor’s note: For several years now, Mentor Graphics has evangelized about the critical need for assembly design kits to enable commercialization of high-density advanced packaging technologies, such as fine line and space fan-out, 2.5D and 3D IC packages. With this week’s introduction of a unique, end-to-end, high-density advanced packaging (HDAP) design flow, combined with the launch of an... »

Will IoT be the Next Killer App for Semiconductors?

Will IoT be the Next Killer App for Semiconductors?

At the end of April, I attended the Internet of Things (IoT) Developers Conference at the Santa Clara Convention Center. Because our semiconductor industry is expecting that IoT applications will significantly contribute to revenue growth, I wanted to get the latest about: If, how, when, why and for which applications IoT designs will be introduced and ramped into high-volume production. General i... »

Part 2: IMAPS DPC 2017 Covers Range of High-tech Topics, including EDA

Part 2: IMAPS DPC 2017 Covers Range of High-tech Topics, including EDA

The keynotes outlined in Part 1 of IMAPS DPC 2017 Covers Range of High-tech Topics, including EDA were obviously very important, but a relatively small part of the entire conference. After the two keynotes on Tuesday morning, I listened to YOLE’s presentation, delivered by Santosh Kumar, and learned that the three big memory vendors (Samsung, Micron, and Hynix) jointly hold over 200 TSV patents ... »

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