Increasing the Conductive Density of Power Packaging
Mar 03, 2021 · By Shaun Bowers · 3D In-Depth, Materials, Processes and Technology
Latest Posts
Temporary Wafer Bonding System Is Based On Electrostatics, Not Adhesives
Temporary wafer bonding is widely employed in semiconductor device fabrication and in semiconductor device packaging applications, particularly now that changes...
Temporary Bonding and Mold Process to Enable Next-Gen FOWLP
Temporary wafer bonding processes were initially developed for enabling three-dimensional (3D) stacked integrated circuits (ICs). For example, dies can be...
A Look Inside The 3D Technology Toolbox For STCO
System-technology co-optimization (STCO) – enabled by 3D integration technologies – is seen as a next ‘knob’ for continuing the scaling...
Addressing the Challenges of Surface Preparation for Advanced Wafer Level Packaging
As the semiconductor industry shifts focus from CMOS scaling to heterogeneous integration, the importance of surface preparation and wafer cleans...
CoolCube™: More than a True 3D VLSI Alternative to Scaling
Almost four years ago, we published an article titled “CoolCube™: A True 3DVLSI Alternative to Scaling” on 3D InCites. It...
Replacing NMP: Are You Ready?
NMP is an abbreviation for N-methyl-2-pyrrolidone (other synonyms are 1-Methyl-2-pyrrolidone and 1-Methyl-2-pyrrolidinone) (Figure 1). NMP has proven itself as an...
The Fundamentals and Early History of Quantum Mechanical Tunneling
The mid-1920’s were the miracle years for quantum mechanics. The “Old Quantum Theory” originating with Niels Bohr, had reached crisis point by the...
The Triumph of Quantum Mechanics at the Heart of Solid-State Data Storage
If all the data sent worldwide each day on the internet were burned on to CDs and these were then piled one... Integrated Solid-state Capacitors Based on Carbon Nanostructure
The constant demand for miniaturization, added functionality and increased performance of electronic devices systematically drives higher integration by adding more... 3D Systems-on-Chip: Clever Circuit Partitioning To Extend Moore’s Law
In recent years, the technology of 3D integration has evolved into an economically interesting road. In particular, the technology is...
The Dual-Gate Thin Film Transistor for 3D Dynamic and Flash Memory
Data is now the world’s most valuable resource. Solid-state storage of data is driving an innovation revolution built upon 50 years...
Lam Research: SABRE 3D
SABRE® 3D is a next-generation electroplating product designed to meet leading-edge production requirements for advanced packaging applications. This product leverages proprietary... Nordson ASYMTEK: Programmable Tilt + Rotate 5-Axis Fluid Dispenser
Nordson ASYMTEK’s programmable Tilt + Rotate 5-Axis Fluid Dispenser dispenses using 5 axes instead of 3. The X and Y... SPTS: Sigma fxP PVD with Multi-Wafer Degas
SPTS’s Sigma® fxP, is a well established PVD system used in advanced packaging applications such as UBM and RDL. It... KLA-Tencor: CIRCL-AP™
CIRCL-AP™ is a cluster tool with multiple modules, covering all-surface inspection, metrology and review at high throughput for efficient advanced...
EV Group: GEMINI®FB XT Automated Production Fusion Bonding System
The GEMINI®FB XT fusion wafer bonding platform features up to a 3X improvement in wafer-to-wafer bond alignment accuracy as well...
Heterointegration Spoor in the 2015 Analog, MEMS and Sensor Startups to Watch, Part 3
In Parts 1 and 2 of this series, I drew your attention to what Peter Clarke, writing in EETimes on...
Executive Viewpoint: Invensas Opens its Toolbox of Interconnect Options
We’ve heard it expressed many times whenever there’s a new interconnect technology vying for adoption: manufacturers will select the best...
SSEC: Wet Etch Process for TSV Reveal
SSEC’s wet TSV reveal process achieves -/+ 0.7% Si thickness uniformity under the appropriate post grinding conditions with fast throughput....