Processes and Technology

The Dual-Gate Thin Film Transistor for 3D Dynamic and Flash Memory

The Dual-Gate Thin Film Transistor for 3D Dynamic and Flash Memory

Data is now the world’s most valuable resource. Solid-state storage of data is driving an innovation revolution built upon 50 years of progress. Here we look at the dual-gate thin film transistor (DG-TFT), an extremely versatile solid-state data storage device that can be used in monolithic 3D as either a flash memory or a dynamic memory element. It has the potential to provide a path not only ... »

Heterointegration Spoor in the 2015 Analog, MEMS and Sensor Startups to Watch, Part 3

Heterointegration Spoor in the 2015 Analog, MEMS and Sensor Startups to Watch, Part 3

In Parts 1 and 2 of this series, I drew your attention to what Peter Clarke, writing in EETimes on 02 January 2015, called the “15-in-15: Analog, MEMS and sensor startups to watch in 2015.” If we were to look for heterointegration spoor amongst Peter’s 15 notable startups what would we find? The first “10-in-15” companies profiled in Parts 1 and 2, namely Cambridge CMOS Sensors; Chirp Mi... »

Executive Viewpoint: Invensas Opens its Toolbox of Interconnect Options

Executive Viewpoint: Invensas Opens its Toolbox of Interconnect Options

We’ve heard it expressed many times whenever there’s a new interconnect technology vying for adoption: manufacturers will select the best performing option at the lowest cost to do the job. However, as performance requirements reach previously un-anticipated levels, pitch requirements become tighter, and density requirements become higher, the job of the packaging engineer to provide increased... »

2013 ITRS Roadmap Calls for 3D Power Scaling; Monolithic 3D Gains Traction

2013 ITRS Roadmap Calls for 3D Power Scaling; Monolithic 3D Gains Traction

At the beginning of April, the Semiconductor Industry Association released the 2013 International Roadmap for Semiconductors (ITRS), which has traditionally served as a guide for “assessing and improving the future of semiconductor technology,” according to Brian Toohey, president and CEO, Semiconductor Industry Association. Sponsored by five regions of the world including Europe, Japan, Korea... »

Latest Developments in Cleans for TSVs and Cu Bumps

Latest Developments in Cleans for TSVs and Cu Bumps

At IMAPS DPC 2014, which took place March 11-13, 2014, in Fountain Hills, AZ, there were several presentations focused on new developments in cleans for TSVs and Cu bumps for 2.5D and 3D IC processes. Cleans has become increasingly important as bump pitches are reduced and TSVs have higher aspect ratios. It’s not just about being clean enough, but also about surface preparation for the next proc... »

TCI for Wireless Chip Stacking; Progress for Monolithic 3D

TCI for Wireless Chip Stacking; Progress for Monolithic 3D

Every once in a while, it’s important to remember that through silicon vias (TSVs) might not be the only game in town. While many continue to forge ahead, with commercialization so close we can taste it, others are already moving on to the next thing or looking for alternatives. Will these beat TSVs to the finish line? Not likely, considering this industry’s slow-to-adopt culture. But it’s s... »

Polymer filled TSVs, Courtesy of EV Group

Polymer Filled TSVs: Solving the Cu Stress Issue

I’ve been on a quest to find out more about EV Group’s new polymer filled TSVs since they first announced it in September. According to a company press release, NanoFill™ process is said to provide “void-free via filling of very deep trenches and high-aspect ratio (HAR) structures, and is suitable for all common polymeric dielectrics—offering a highly flexible, low-cost and production-re... »

The Back Story on Besang’s True 3D ICs

The Back Story on Besang’s True 3D ICs

BeSang Inc, a fabless semiconductor company in Beaverton, OR, has been on my 3D IC radar since 2008, when I first edited a 3D technology cover feature in Advanced Packaging Magazine, written by George C. Riley, that included a status report on BeSang’s TRUE 3D ICs™, which had just been demonstrated. What I didn’t understand then, that I know now, was that this was an example of what we today... »

Image Courtesy of TSMC Ltd.

What Node Names Really Mean; The TB/DB Saga continues; HMC update

Did you know that when foundries talk about 14nm and 16nm node chips, these devices are in reality no denser than their 20nm predecessors? Or that a particular node name does not reflect the size of any particular chip feature, as it once did? Or that since 2007, the doubling of transistors on a chip has actually been more like 1.6x the number of the previous generation? According to a recent feat... »

TSMC 3D IC Reference Flows; A Leap Forward for the HMC

TSMC 3D IC Reference Flows; A Leap Forward for the HMC

Big news for 3D ICs this week as TSMC and its OIP Ecosystem Partners announce the release of silicon-validated reference flows for both 3D IC stacks and 16nm FinFETS (everyone else puts the 16nm FinFETS first, but I’m most excited about the 3D IC news.) According to Peter Clarke in EETimes, “silicon validation of these flows signifies the opening up of the manufacturing processes for the desig... »

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