Sitaram R. Arkalgud, Ph.D.
Sitaram Arkalgud is driving the application of Xperi bonding technologies (ZiBond® and DBI ®) in numerous 3D products across the industry. Prior to this role, he led the 3D group as VP, 3D Technology and Portfolio at Invensas. Before joining Xperi (Invensas), he started and led 3D-IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for TSV, Cu/Cu wafer/die bonding and wafer thinning for 3D IC. Previously, Sitaram worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. He is the author of several publications and holds 42 U.S. patents. Sitaram holds master’s and Ph.D. degrees in materials engineering from Rensselaer Polytechnic Institute in Troy, N.Y., and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College (NIT-K), Surathkal, India.
Global director of strategic marketing at DowDupont, Rozalia Beica is an international award (R&D 100) winning scientist with over 60 publications and several patents. For more than 16 years, Rozalia has been involved in the research, application and strategic marketing of Advanced Packaging and 3D IC technologies, with global leading responsibilities at Yole Dévelopeement, and for materials (Rohm and Haas), equipment (Semitool, Applied Materials, Lam Research) and device manufacturing (Maxim IC) organizations. She has a Global Executive MBA from IE Business School (Spain), M. Sc. In Management of Technology from KW University (USA) and a B.Sc/M.Sc in Chemical Engineering from Polytechnic University “Traian Vuia” (Romania)
Pascal Couderc, R&PD Manager, 3D PLUS, France
Research and Development Manager at 3D PLUS since 2002, Pascal Couderc has led the development of 3D technologies, such as wire-free die-on-die (WDoDTM) technology for space, medical and industrial applications. He has been involved in more than ten European projects and has authored or co-authored publications and patents in the field of 3D technology. Prior to 3D Plus, he spent 11 years at Alcatel Group as an engineering and technology specialist in the field of thin films, printed circuit boards and hybrid modules for microwave applications. He spent the first five years of his career at Airbus Group as a thin film application engineer. Pascal has a Ph.D. in Material Sciences with a specialty in thin-film technology from Nantes University (France).
Yann Guillou, Marketing & Sales Director, Trymax Semiconductor, Netherlands
Yann Guillou is the Marketing & Sales Director at Trymax, a semiconductor plasma-based equipment company. Yann started his career at STMicroelectronics in new technology marketing and continued at ST-Ericsson as a member of the CTO office, promoting FOWLP and TSV technologies for wireless applications. Then he joined SEMI as Business Development Manager to grow the membership base in Europe and founded new flagship events in the field of 3D Packaging and MEMS. Then, he went back to a privately-owned company, UnitySC, to manage their global marketing before joining Trymax. Yann holds an MSc in materials and nanotechnology from the National Institute of Applied Sciences (France) and a master in management of technology and innovation from Grenoble Business School (France).
Dr. Phil Garrou, Microelectronic Consultants of NC, USA
Dr. Phil Garrou is a subject matter expert for DARPA and runs his consulting company Microelectronic Consultants of NC in the RTP NC area. He retired from Dow Chemical in 2004 as Global Director of Technology for their Advanced Electronic Materials business unit. Phil has served as Technical VP and President of both IEEE EPS and IMAPS and is a Fellow of both organizations. He has edited several microelectronic texts including McGraw Hill’s “Multichip Module Handbook” and Wiley VCH’s “Handbook of 3D Integration”. He has won the Milton Kiver Award for Excellence in Electronic Packaging (1994); the Fraunhofer International Adv. Packaging Award (2002); the IEEE CPMT Sustained Technical Achievement Award (2007) , the IMAPS Ashman Award (2000) and most recently the American Chemical Society Award for Team Innovation (2017). His weekly publication Insights From the Leading Edge (IFTLE) has been a weekly advanced packaging blog since 2010.
Erik Jan Marinissen, Scientific Director at imec, Belgium
Erik Jan Marinissen is Scientific Director at the world-renowned research institute imec in Leuven, Belgium, where he is responsible for research on test and design-for-test, covering topics as diverse as TSV-based 3D-stacked ICs, CMOS technology nodes below 10nm, silicon photonics, and STT-MRAMs. In addition, he is a Visiting Researcher at Eindhoven University of Technology in the Netherlands. Previously, he worked at NXP Semiconductors and Philips Research Laboratories in Eindhoven, Nijmegen, and Sunnyvale. Marinissen holds an MSc degree in Computing Science (1990) and a PDEng degree in Software Technology (1992), both from Eindhoven University of Technology. He is (co-)author of 275+ journal and conference papers, co-editor of Wiley´s “Handbook of 3D Integration”, Vol. 4, and (co-) inventor on 18 granted US/EP patent families. Additionally, he is the recipient of numerous industry awards, was recently recognized as being the most-cited author of ITC papers over the period 1995-2019, serves on several editorial boards, and has chaired numerous workshops on 3D Test. Marinissen is a member of the IEEE’s Test Technology Standardization Committee and served as editor-in-chief of IEEE Std 1500™-2005 on embedded-core test, and as founder/chair (currently vice-chair) of the IEEE Std 1838™-2019 on 3D-SIC test access. He is an IEEE Fellow, Golden Core Member of IEEE Computer Society, and serves on the Board of Governors of the IEEE Computer Society (2019-2021).
Peter Ramm, Head of Strategic Projects, Fraunhofer EMFT, Germany
As head of Strategic Projects at Fraunhofer EMFT, Peter Ramm is responsible for initiation and steering of strategic projects and international research co-operations. He received Masters and Dr. rer. nat. Degrees from the University of Regensburg and subsequently worked for Siemens in their DRAM facility where he was responsible for the overall process integration with a focus on backend-of-line. In 1988, he joined Fraunhofer Munich, working mainly on integration technologies for innovative devices and heterogeneous systems including the development of 3D TSV processes. Peter Ramm is the author of over 120 publications and 36 issued patents (Europe, Japan, USA). He received the “Ashman Award” in 2009 from the International Electronics Packaging Society (IMAPS) and the 2020 IEEE Technical Field Award “For Pioneering Contributions Leading to the Commercialization of 3D Wafer and Die level Stacking Packaging”. He is Senior Member IEEE, IMAPS Fellow, and Life Member. Peter Ramm serves as chair of the IEEE Technical Committee 3D/TSV and is a member of several roadmap initiatives as the International Roadmap for Devices and Systems IRDSTM (IFT “More Moore”) and the Heterogeneous Integration Roadmap HIR (TWG “Interconnects”).
Herb Reiter, Founder, eda2asic Consulting, USA
After more than 20 years in technical and business roles at semiconductor and EDA companies, Herb Reiter founded eda2asic Consulting, Inc. in 2002 to focus on increasing the cooperation between EDA suppliers and ASIC vendors. In this role, Herb introduced innovative IC design tools to the major semiconductor vendors worldwide. In 2008 he expanded his scope into Multi-die ICs. As chair of the GSA’s 3D-IC Working Group and as SEMATECH business development consultant, he broadened his horizon to include die-package-board design challenges as well as Assembly Design Kits (ADKs), to accurately convey characteristics of IC packaging materials and interposers. Herb also consulted with Si2, to encourage the development and standardization of data exchange formats for Multi-die IC design flows. He also worked with the newly formed Electronic System Design (ESD) Alliance (formerly EDAC), to accelerate market acceptance of Multi-die ICs and die-level IP, the essential building blocks for economical System Scaling.
Mark Scannell, Director of Business Development Silicon Component Division, Leti, France
Mark Scannell has an engineering degree from National University Ireland. He has 25 years of experience in the electronics and semiconductor industry. Starting his career as an electro-mechanical design engineer in 1989; he subsequently worked for one of the world’s leading semiconductor equipment suppliers in various engineering positions and as a technology business director. Mark has lived in several countries; notably Japan, Germany, USA, and France. He joined CEA – Léti in 2005. Mark’s current position is Business Development Director where his responsibilities include business development for silicon components, industrial contracts, and IP management.
Dr. Maaike M. Visser Taklo, QA Manager, Disruptive Technologies, Norway
At Disruptive Technologies, Maaike M. Visser Taklo is employed as Quality Assurance Manager and has the responsibility for reliability studies on their world’s smallest IoT sensors. Previously, she served as Chief Scientist at SINTEF Digital in Norway at the Department of Smart Sensor Systems which she joined in 2010. Within this department, she was Research Manager for the group “Advanced Packaging and Interconnects”. From 1998 until 2010 she was employed at the Department of Microsystems within SINTEF Digital where she worked on MEMS processing and was responsible for their wafer-level bonding activities. She received her Ph.D. degree in Physical Electronics from the University of Oslo in 2002 for her thesis entitled “Wafer bonding for MEMS”. She is the author or co-author of more than 50 papers and edited the book “Handbook of Wafer Bonding” (Wiley, 2012) together with P. Ramm and J-Q Lu. She has been part of the management team of several European projects and regularly performs proposal and project reviews for the European Commission.
E. Jan Vardaman, president and founder of TechSearch International, Inc., USA
E. Jan Vardaman founded TechSearch International Inc. in 1987, and since then has provided licensing and consulting services in semiconductor packaging. She is the co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbunsha), a columnist with Circuits Assembly/Printed Circuit Board Fabrication, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a member of IEEE CPMT, SMTA, MEPTEC, IPC, IMAPS, and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium. She has made numerous presentations on developments in advanced packaging.
Paul Werbaneth, Independent Consultant and Writer
Paul Werbaneth is a long-time Contributing Editor at 3D InCites. Paul received a B.S. degree in chemical engineering from Cornell University, Ithaca, NY, USA, and recently completed studies in spoken Japanese from the Cornell Summer FALCON Program, and in marketing strategy, also through Cornell. Since entering the semiconductor industry in 1980, Paul has been a hands-on Photolithography Process Sustaining Engineer in an Intel wafer fab; a Senior Plasma Etch Process Engineer with Hitachi High Technologies; the Country Manager for Tegal Japan Inc.; the Vice President of Marketing and Applications at Tegal Corporation; a Business Development Manager at EV Group; an independent consultant and writer; the Global Product Marketing Director at Intevac, Inc.; and Global Product Manager at Nor-Cal Products, Inc. Paul is a member of the SEMI Advanced Semiconductor Manufacturing Conference Steering Committee and was the SEMI ASMC 2004 Conference Co-Chair. Active in the Northern California Chapter of the American Vacuum Society for many years, Paul was Program Chair for the NCCAVS Technical Symposium 2019 and is the Chapter Chair for 2019. Paul is also a Guest Editor of IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING; wrote the contributed chapter on TSV etching in the book “3D Integration for VLSI Systems,” and has written or co-written an extensive number of articles, papers, and blogs regarding the semiconductor capital equipment business, advanced packaging, and various aspects of semiconductor manufacturing.
M. Juergen Wolf, Head of Division Wafer Level System Integration, Fraunhofer IZM-ASSID, Germany
M. Juergen Wolf studied electrical engineering and after an industrial career, he joined Fraunhofer Institute for Reliability and Micro-integration (IZM), Berlin in 1994 working in the field of wafer-level packaging and System in Package (SiP). Since 2011 he is head of department Wafer Level System Integration and also responsible for the management of ASSID – “All Silicon System Integration Dresden-ASSID” with its 300 mm 3D Wafer Level Integration line. He is also involved in and leading a number of research projects on the national, European and international level. Wolf is, among others, a European representative in the technical working group Assembly & Packaging of ITRS, a board member of EURIPIDES and JISSO as well as a member of IEEE and SMTA. He has authored and co-authored numerous scientific papers and reports in the field of microelectronic packaging and holds a number of patents.