3D InCites Technical Advisory Board

Sitaram R. Arkalgud, Ph.D., VP of 3D Technology, Invensas Corp. San Jose, CA

Arkalqud, SitaramSitaram Arkalgud is Vice President of 3D Technology at Invensas Corporation, a complete Interconnectology solutions provider for advanced mobile applications. Previously, Arkalgud started and led 3D IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for 3D interconnects. In addition, he has worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. Arkalgud holds a doctorate and master’s degree in materials engineering from Rensselaer Polytechnic Institute in Troy, NY, and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Suratkal, India. He is the author of several publications and holds 14 U.S. patents.

rbeicaRozalia Beica, CTO, Dow Electronic Materials
Rozalia Beica is global director for new business development at Dow Electronic Materials. She is an international award (R&D 100) winning scientist with over 60 publications and several patents. For more than 16 years, Rozalia has been involved in the research, application and strategic marketing of Advanced Packaging and 3D IC technologies, with global leading responsibilities at Yole Dévelopeement, and for materials (Rohm and Haas), equipment (Semitool, Applied Materials, Lam Research) and device manufacturing (Maxim IC) organizations. She has a Global Executive MBA from IE Business School (Spain), M. Sc. In Management of Technology from KW University (USA) and a B.Sc/M.Sc in Chemical Engineering from Polytechnic University “Traian Vuia” (Romania)

Pascal Couderc, R&D Manager, 3D PLUS
Research and Development Manager at 3D PLUS since 2002, Pascal Couderc has led the development of 3D technologies, such as wire-free die-on-die (WDoDTM) technology for space, medical and industrial applications. He has been involved in more than ten European projects and has authored or co-authored publications and patents in the field of 3D technology. Prior to 3D Plus, he spent 11 years at Alcatel Group as engineering and technology specialist in the field of thin films, printed circuit boards and hybrid modules for microwave applications. He spent the first five years of his career at Airbus Group as a thin films application engineer. Pascal has a Ph.D. in Material Sciences with a specialty in thin film technology from Nantes University (France).

Yann Guillou, Marketing Manager, UnitySC, France

P1010806bis5_JPG_thumb_156Yann Guillou is the marketing manager at UnitySC in Grenoble, France, where he is responsible for UnitySC global marketing strategy, product, and marketing communications. Previously, he served as Business Development Manager at SEMI Europe Grenoble Office, where he was responsible for the development of SEMI activities in France & Southern Europe in Semiconductor, PV, and Emerging markets and the coordination of SEMI standard activities in Europe. Previously, Yann worked on Advanced Packaging activities within the Back-End Sourcing and CTO & Strategic Planning office of ST-Ericsson. His main interest was 3D integration and TSV. He started his career at CEA-Leti before joining ST Microelectronics and successively worked at ST-NXP Wireless and ST-Ericsson. Yann holds an MS in materials and nanotechnology from the National Institute of Applied Sciences and a master of management of technology and innovation from Grenoble Business School.

Erik Jan Marinissen, Principal Scientist at IMEC, Leuven, Belgium

Erik Jan Marinissen is Principal Scientist at the world-renowned research institute imec in Leuven, Belgium, where he is responsible for research on test and design-for-test, covering topics as diverse as TSV-based 3D-stacked ICs, silicon photonics, CMOS technology nodes below 10nm, and STT-MRAMs. In addition, he is Visiting Researcher at the Eindhoven University of Technology, the Netherlands. Previously, he worked at NXP Semiconductors and Philips Research Laboratories in Eindhoven. Marinissen holds an MSc degree in Computing Science (1990) and a PDEng degree in Software Technology (1992), both from Eindhoven University of Technology. He is (co-)author of 280+ journal and conference papers and (co-) inventor on twelve granted US/EP patent families. Additionally, he is the recipient of numerous industry awards and serves on a multitude of editorial boards and has chaired numerous workshops on 3D Test.

Peter Ramm, Department Head, Heterogenous Systems Integration, Fraunhofer EMFT, Munich, Germany

Foto PeterDr. Peter Ramm is responsible for the key competence “Si Processes, Device, and 3D Integration”. He received physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for more than 25 years on 3D integration technologies. Peter Ramm is author or co-author of over 100 publications and 24 patents. He received the “Ashman Award 2009” from the International Electronics Packaging Society (IMAPS) “For Pioneering Work on 3D IC Stacking and Integration and leading-edge work on SiGe and Si technologies”. Peter is Fellow and Life Member of IMAPS, organizing committee and founding member of IEEE 3DIC conference and co-editor of Wiley´s “Handbook of 3D Integration”, vol. 1, 2 & 3 and Wiley´s “Handbook of Wafer Bonding”.

Herb Reiter, Founder, eda2asic Consulting, Palo Alto, CA

HerbnewAfter more than 20 years in technical and business roles at semiconductor and EDA companies, Herb Reiter founded eda2asic Consulting, Inc. in 2002 to focus on increasing the cooperation between EDA suppliers and ASIC vendors. In this role, Herb introduced innovative IC design tools to the major semiconductor vendors worldwide. In 2008 he expanded his scope into Multi-die ICs. As chair of the GSA’s 3D-IC Working Group (2008-2011) and as SEMATECH business development consultant (2012 + ‘13), he broadened his horizon to include interposers and 3D-ICs technology, semiconductor materials as well as manufacturing, metrology and test equipment. In 2014 + ’15 Herb consulted with Si2, to encourage development and standardization of data exchange formats for Interposer and 3D-IC design flows. Since early 2016 he is consulting with the newly formed Electronic System Design Alliance (formerly EDAC), to accelerate market acceptance of Multi-die ICs, the essential building blocks for the emerging System Scaling methodology. 

Mark Scannell, Director Business Development Silicon Component Division, Leti, Grenoble, France

Mark ScannellMark Scannell has an engineering degree from National University Ireland. He has 25 years experience in the electronics and semiconductor industry. Starting his career as an electro-mechanical design engineer in 1989; he subsequently worked for one of the world’s leading semiconductor equipment suppliers in various engineering positions and as a technology business director. Mark has lived in several countries; notably Japan, Germany, USA, and France. He joined CEA – Léti in 2005. Mark’s current position is Business Development Director where his responsibilities include business development for silicon components, industrial contracts, and IP management.


Dr. Maaike M. Visser Taklo, Chief Scientist, SINTEF Digital, Oslo, Norway
Dr. Maaike M. Visser Taklo is a Chief Scientist at SINTEF Digital in Norway at the Department of Smart Sensor Systems which she joined in 2010. Within this department, she is Research Manager for the group “Advanced Packaging and Interconnects”. From 1998 until 2010 she wa employed at the Department of Microsystems within SINTEF Digital where she worked on MEMS processing and was responsible for their wafer level bonding activities. She received her Ph.D. degree in Physical Electronics from the University of Oslo in 2002 for her thesis entitled “Wafer bonding for MEMS”. She is the author or co-author of more than 50 papers and edited the book “Handbook of Wafer Bonding” (Wiley, 2012) together with P. Ramm and J-Q Lu. She has been part of the management team of several European projects and regularly performs proposal and project reviews for the European Commission.

E. Jan Vardaman, president and founder of TechSearch International, Inc., Austin, TX

E. Jan Vardaman, TechSearch InternationalE. Jan Vardaman founded TechSearch International Inc. in 1987, and since then has provided licensing and consulting services in semiconductor packaging. She is the co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbunsha), a columnist with Circuits Assembly/Printed Circuit Board Fabrication, and the author of numerous publications on emerging trends in semiconductor packaging and assembly.  She is a member of IEEE CPMT, SMTA, MEPTEC, IPC, IMAPS, and SEMI.  She was elected to two terms on the IEEE CPMT Board of Governors.  Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.  She has made numerous presentations on developments in advanced packaging.


Paul Werbaneth, Global Product Marketing Director, Intevac, Inc.
PFW Headhsot 2015
Paul Werbaneth is the Global Product Marketing Director at Intevac, Inc. Since entering the semiconductor industry in 1980 he has been a hands-on Photolithography Process Sustaining Engineer in an Intel wafer fab; a Senior Plasma Etch Process Engineer with Hitachi High Technologies; the Country Manager for Tegal Japan Inc.; the Vice President of Marketing and Applications at Tegal Corporation; a Business Development Manager at EV Group; and an independent consultant and writer. Paul is a member of the SEMI Advanced Semiconductor Manufacturing Conference steering committee and was the ASMC 2004 Conference Co-Chair. He also serves on the steering committee for the NCCAVS Thin Film User Group.  Paul’s writing activities include his frequent contributions on heterogeneous integration and 2.5-D/3-D IC technology and commercialization to 3D InCites; his work as a Guest Editor for IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING; the contributed chapter on TSV etching in the book 3D Integration for VLSI Systems. Follow him on Twitter @PFWerbaneth.

M. Juergen Wolf, Head of Division Wafer Level System Integration, Fraunhofer IZM-ASSID
Wolf2012M. Juergen Wolf studied electrical engineering and after an industrial career, he joined Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin in 1994 working in the field of wafer level packaging and System in Package (SiP). Since 2011 he is head of department Wafer Level System Integration and also responsible for the management of ASSID – “All Silicon System Integration Dresden-ASSID” with its 300 mm 3D Wafer Level Integration line. He is also involved in and leading a number of research projects on the national, European and international level. Wolf is, among others, a European representative in the technical working group Assembly & Packaging of ITRS, a board member of EURIPIDES and JISSO as well as a member of IEEE and SMTA. He has authored and co-authored numerous scientific papers and reports in the field of microelectronic packaging and holds a number of patents.