An EDA Perspective on Today’s Advanced Packaging
Jun 22, 2020 · By Herb Reiter · 3D In Context, Blogs, Design
Latest Posts
Striking the Right Chord for Chiplet Integration
The growing digitalization of our society has made our lives connected and, in many aspects, easier. But the digital revolution...
An Update on the Fan-out Panel-Level Packaging Consortium
One topic that has been under hot debate in the semiconductor advanced packaging sector for the past few years is...
EDPS 2017: NOT the usual Electronic DESIGN Process Symposium
When planning the 24th EDPS, the organizing committee, chaired by Shishpal Rawat, former Intel executive, took a number of bold...
Executive Viewpoint: Breaking The Chicken and Egg Cycle for HDAP
For several years now, Herb Reiter, eda2asic, and John Ferguson, Mentor Graphics, have been evangelizing about the necessity of assembly...
Mentor Graphics: Xpedition Package Integrator
Xpedition® Package Integrator provides a holistic co-design methodology that automates planning and optimization of connectivity from a chip through multiple...
Executive Viewpoint: Inside a Multi-Project Wafer Program for 3D Integration
Multi-project wafer (MPW) programs have long been considered an economical way to integrate different IC designs from various teams to...
Executive Viewpoint: An Interposer Integration and 3D IC Success Story
While the rest of the industry anticipates the coming of 3D ICs, and along with it the long anticipated return...
Executive Interview: Si2 Aims to Boost Confidence in Designing 3D ICs
There’s no doubt left in the minds of semiconductor device manufacturers that the processes required to build interposer-based and 3D...
3D By Design: A Blog By and For the 3D Design Community
Earlier this year, I published an open letter to chip and system-level designers regarding 3D integration, suggesting they consider 3D...
TSV MEOL Process Flow for Mobile 3D IC Stacking
Moore’s law is approaching physical limitations of CMOS scaling, and three dimensional (3D) integration technologies have been proposed as solutions....
E-System Design: Sphinx 3D Path Finder (“3DPF”) V3.0
The Sphinx 3D Path Finder (3DPF) is an exploration tool enabling fast test case creation and analysis for silicon and...
An Open Letter to Chip and System-level Designers Regarding 3D Integration
Dear Chip and System-level Designers, Allow me to introduce myself. My name is Françoise von Trapp, and I am known...
3D Integration Workshop Faces Reliability Challenges Head On
The Friday 3D Integration Workshop at DATE 2014 once again found me among friends, as an intimate group of about...
Making Progress with 3D IC Design and Test
Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for 2.5D...
3D IC Design: Outlook for 2014
To date we at Mentor Graphics have seen a handful of 3D IC design releases, and even more customer evaluations....
2.5D Interposer Innovations from Silex and eSilicon
2.5D interposers sparked a good amount of discussion at this year’s 3D ASIP conference (December 11-13, 2013, Burlingame CA), with...
Part 2: 3D NAND Flash: Towering Spires or Costly Canyons?
In my last blog posting I went over the cost aspects of the Samsung-Toshiba 3D NAND approaches. The conclusion is...
TSMC 3D IC Reference Flows; A Leap Forward for the HMC
Big news for 3D ICs this week as TSMC and its OIP Ecosystem Partners announce the release of silicon-validated reference...
And a Good Time was had by All – 3D InCites Awards Breakfast, 2013
Despite the chilly San Francisco morning temperatures, a sizable crowd of 2.5D and 3D enthusiasts gathered at the Impress Lounge...