At this year’s International Wafer-level Packaging Conference, almost 1000 semiconductor experts from all parts of the supply chain gathered at the DoubleTree Hotel in San Jose from October 23 to 25. Among them were also several electronic design automation (EDA) experts who discussed how to streamline die-package-board co-design. They explained how EDA tools enable higher performance per Watt a... »
One topic that has been under hot debate in the semiconductor advanced packaging sector for the past few years is fan-out panel-level packaging (FOPLP). In theory, the concept of taking fan-out from a 300-mm reconstituted wafer to a large panel format as a way to lower costs seems simple, and even the logical step. It’s not. Skeptics, many burned by the same low-cost advantage argument for inv... »
When planning the 24th EDPS, the organizing committee, chaired by Shishpal Rawat, former Intel executive, took a number of bold steps EDPS was traditionally held in the spring. We moved EDPS to the fall because that’s a time when more new IC projects are being planned. After many years of holding it in Monterey, we moved EDPS to Milpitas to make it more easily accessible for Silicon Valley folks... »
For several years now, Herb Reiter, eda2asic, and John Ferguson, Mentor Graphics, have been evangelizing about the necessity of assembly design kits (ADK), similar to the process design kits (PDKs) for chip designers, to help drive ecosystem capabilities for what is collectively now being called high density advanced packaging (HDAP), comprising 2.5D IC, 3D IC and high density fan-out wafer... »
Multi-project wafer (MPW) programs have long been considered an economical way to integrate different IC designs from various teams to produce IC design prototypes and low volumes. Because IC fabrication costs are extremely high, it makes sense to share mask and wafer resources in this way. MPWs were historically used for 2D designs, but in 2009, Tezzaron Semiconductor launched an MPW for DARPA to... »
While the rest of the industry anticipates the coming of 3D ICs, and along with it the long anticipated return on investment that goes with it, one small Silicon Valley fabless has been chugging along, already reaping the benefits of interposer integration and 3D IC technologies. I first heard Farhang Yazdani, CEO, BroadPak present during a GSA 3DIC Working Group meeting on 3D IC readiness, and th... »
There’s no doubt left in the minds of semiconductor device manufacturers that the processes required to build interposer-based and 3D IC devices are matured and ready for production. However, the jury is still out in the design community because designing 3D ICs still poses a challenge. Si2 has set out to change that and bring confidence to the minds of chip and system-level designers. Steve Sc... »
Earlier this year, I published an open letter to chip and system-level designers regarding 3D integration, suggesting they consider 3D integration technologies as a solution to dealing with the increasing complexity of SoC designs. The post was inspired by my attendance at the Design and Test Europe (DATE 2014) conference, where I moderated a session on system on chip (SoC) design complexity, and ... »
Moore’s law is approaching physical limitations of CMOS scaling, and three dimensional (3D) integration technologies have been proposed as solutions. Wide band transmission between logic and memory is becoming indispensable for not only mobile products, but also other products related to network systems such as servers and data centers. These days, 3D integration with Through Silicon Vias (T... »
Dear Chip and System-level Designers, Allow me to introduce myself. My name is Françoise von Trapp, and I am known in the semiconductor industry as “The Queen of 3D”. This is because I have held a deep interest in 3D integration technologies, and have devoted the past 7+ years to following the development of the processes involved from proof of concept through to manufacturability, and report... »
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