Forging a New Future for 3D IC Design and Architecture
Oct 26, 2022 · By Bob Smith · 3D In-Depth, Design
Latest Posts
Thermal Analysis Techniques to Improve High Density Semiconductor System Performance
Thermal problems in semiconductor electronic systems often go unnoticed and cause failures. Although thermal problems can be understood and avoided...
Considerations in Power Amplifier Package Design
Understanding the role of compromises and trade-offs in the design process Electronic packages serve many purposes including protecting, connecting, and...
Design-for-test for 3D IC Designs Comes of Age
In the era of more-than-Moore, 3D IC is the new scaling approach adopted by the marketplace. Progress has been made...
Let’s Start the ESD Alliance – 3D InCites Conversation!
This post kicks off what I expect to be a regular series of blogs that will help tie the system...
EDPS 2020: An Inside Look at the Manufacturing-centric Presentations
Like many other industry conferences, the Electronic Design Process Symposium (EDPS 2020) had to go virtual. Not only did it...
DAC 2020 Addresses Chiplet Design and Integration
In the early days of ASIC technology, only logic library elements and basic I/Os with up to 10s of transistors...
An EDA Perspective on Today’s Advanced Packaging
In my alliance management roles at electronic design automation (EDA) companies, I arranged many presentations to convey the benefits of...
Striking the Right Chord for Chiplet Integration
The growing digitalization of our society has made our lives connected and, in many aspects, easier. But the digital revolution...
An Update on the Fan-out Panel-Level Packaging Consortium
One topic that has been under hot debate in the semiconductor advanced packaging sector for the past few years is...
EDPS 2017: NOT the usual Electronic DESIGN Process Symposium
When planning the 24th EDPS, the organizing committee, chaired by Shishpal Rawat, former Intel executive, took a number of bold...
Executive Viewpoint: Breaking The Chicken and Egg Cycle for HDAP
For several years now, Herb Reiter, eda2asic, and John Ferguson, Mentor Graphics, have been evangelizing about the necessity of assembly...
Mentor Graphics: Xpedition Package Integrator
Xpedition® Package Integrator provides a holistic co-design methodology that automates planning and optimization of connectivity from a chip through multiple...
Executive Viewpoint: Inside a Multi-Project Wafer Program for 3D Integration
Multi-project wafer (MPW) programs have long been considered an economical way to integrate different IC designs from various teams to...
Executive Viewpoint: An Interposer Integration and 3D IC Success Story
While the rest of the industry anticipates the coming of 3D ICs, and along with it the long anticipated return...
Executive Interview: Si2 Aims to Boost Confidence in Designing 3D ICs
There’s no doubt left in the minds of semiconductor device manufacturers that the processes required to build interposer-based and 3D...
3D By Design: A Blog By and For the 3D Design Community
Earlier this year, I published an open letter to chip and system-level designers regarding 3D integration, suggesting they consider 3D...
TSV MEOL Process Flow for Mobile 3D IC Stacking
Moore’s law is approaching physical limitations of CMOS scaling, and three dimensional (3D) integration technologies have been proposed as solutions....
E-System Design: Sphinx 3D Path Finder (“3DPF”) V3.0
The Sphinx 3D Path Finder (3DPF) is an exploration tool enabling fast test case creation and analysis for silicon and...
An Open Letter to Chip and System-level Designers Regarding 3D Integration
Dear Chip and System-level Designers, Allow me to introduce myself. My name is Françoise von Trapp, and I am known...