The Microelectronics Packaging & Test Engineering Council (MEPTEC) held its monthly meeting at SEMI in Milpitas on April 10. Two speakers outlined their companies’ capabilities and demonstrated their own expertise in solving specific industry challenges. Tom Gregorich presented why and how Zeiss supports IC package inspection with 3D X-ray machines, then Sitaram Arkalgud conveyed the benef... »
From February 18 to 21, 2019, Monterey, CA, was again the venue for SEMI’s Flexible Hybrid Electronics (FLEX) and MEMS & Sensors Technical Congress (MSTC), conference. As in previous years, the joint keynotes, 2-track technical sessions, and more than 50 exhibitors demonstrated the synergies between these two industry segments and their fast pace of innovation. The entire conference focused ... »
Santa Clara’s Convention Center was home to DesignCon 2019 from January 29-31, 2019. This conference is well known for showing printed circuit board (PCB) and system designers the latest technology advances, enabling higher performance and lower power and lower cost solutions. Bootcamps, tutorials, keynotes, and many in-depth technical sessions offered engineers up-to-date information to make th... »
Just in case you didn’t have a chance yet to read part 1 of the ISS 2019 blog, covering day 1, it’s posted here. Technology and Manufacturing Trends Day 2 started with a keynote about the magic nanodevices can create, delivered byJo de Boeck, imec’s EVP and chief strategy officer. He emphasized that we need to find smarter ways to compute, store data and connect building blocks. De Boeck ... »
SEMI held its annual Industry Strategy Symposium (ISS 2019) at the Ritz Carlton in Halfmoon Bay, CA January 6-9, 2019. Many high-level executives represented key areas of the electronic products supply chain. Former government officials emphasized that our country’s leaders recognize the strategic importance of semiconductors. The theme of ISS 2019 was: “The Golden Age of Semiconductors: Enabl... »
The Microelectronics Packaging and Test Engineering Council (MEPTEC) held its annual heterogeneous integration symposium at SEMI’s headquarters in Milpitas, CA on December 5, 2018. Many manufacturing and test, as well as electronic design automation (EDA) and IC design experts, got together to present and discuss how to integrate heterogeneous functions in advanced IC packages to better meet cus... »
Wafer and panel-level packaging (WLP/PLP) offers technical and business advantages, compared to traditional IC packages. These cost-effective packaging solutions attracted more than 800 industry experts to the International Wafer Level Packaging Conference (IWLPC 2018) in San Jose’s DoubleTree Hotel at the end of October. In case you were wondering, a multi-die WLP design, created with the tools... »
At this year’s International Wafer-level Packaging Conference, almost 1000 semiconductor experts from all parts of the supply chain gathered at the DoubleTree Hotel in San Jose from October 23 to 25. Among them were also several electronic design automation (EDA) experts who discussed how to streamline die-package-board co-design. They explained how EDA tools enable higher performance per Watt a... »
As I prepared to attend TSMC’s OIP 2018 Forum on October 3, 2018 two emails from TSMC caught my attention. They conveyed the news that TSMC just lowered the entry barrier for SoC design significantly by announcing the OIP Cloud Alliance. This is the latest addition to their four Open Innovation Platform Alliances for EDA, IP, Design Services and Value Chain Aggregators. Having promoted Barcelona... »
The message remains consistent: following Moore’s Law is no longer economical for most IC designs. A major part of the IC value creation is moving from the die to the IC package. Now advanced packaging technologies and materials enable combining multiple dies with heterogeneous functions as well as high-quality passives into one package. This integration increases performance, while significantl... »
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