Devices

Can 3D Super-NAND Improve Cost-per-Bit for 3D NAND?

Can 3D Super-NAND Improve Cost-per-Bit for 3D NAND?

The 3D NAND floodgates just opened a little wider with today’s announcement from BeSang that it has developed 3D Super-NAND technology, based on a monolithic 3D IC process, True 3D™ IC, claiming to be the “lowest cost-per-bit in the NAND market.” With all the recent 3D NAND discussion and announcements about Samsung, Toshiba, and Intel and Micron’s 3D X-point, I wanted to know more. Spec... »

Executive Viewpoint: Invensas Opens its Toolbox of Interconnect Options

Executive Viewpoint: Invensas Opens its Toolbox of Interconnect Options

We’ve heard it expressed many times whenever there’s a new interconnect technology vying for adoption: manufacturers will select the best performing option at the lowest cost to do the job. However, as performance requirements reach previously un-anticipated levels, pitch requirements become tighter, and density requirements become higher, the job of the packaging engineer to provide increased... »

Ye Antique Towers – Samsung’s 3D NAND Flash SSD 850 Pro

Ye Antique Towers – Samsung’s 3D NAND Flash SSD 850 Pro

Samsung’s introduction of its 3D NAND Flash SSD 850 Pro has led to the inevitable hullabaloo. Amid all the fuss, it hasn’t taken long for someone to publish the actual die size. This of course is the golden nugget of information that lays the foundation for any cost analysis. Figure 1 shows a photo, courtesy of PC Perspective, of the actual 86 Gbit 32-layer 2nd generation V-NAND taken on a 3... »

Intel’s Next-Gen Xeon Phi processor to have Micron 3D Memory Inside

Intel’s Next-Gen Xeon Phi processor to have Micron 3D Memory Inside

Somehow in all my preparations for the 2014 3D InCites Awards and planning the schedule for SEMICON West this week, a significant piece of news slipped right by usually alert 3D radar for TWO WHOLE DAYS! On Tuesday, Micron issued a press release announcing a collaboration with Intel to deliver an on-package 3D memory solution for Intel’s next-generation Xeon Phi™ processor, codenamed R... »

3D NAND Flash – Schiltron’s Answer

3D NAND Flash – Schiltron’s Answer

It probably appears that the only 3D technologies vying for 2D NAND’s crown are V-NAND from Samsung and p-BiCS from Toshiba/SanDisk, with their key selling point being their ability to use few lithography steps to build 3D stacked memory. For background, see Jim Handy’s series and mine. Here I will discuss the 3D NAND Flash alternative from my company, Schiltron Corporation, that provides a so... »

Lessons Learned From the Trenches of 3D IC Manufacturing for Sensor Applications

Lessons Learned From the Trenches of 3D IC Manufacturing for Sensor Applications

The technologies are ready, the target high volume  applications for 3D IC manufacturing have been identified, and now it’s about convincing system architects there’s more to gain from designing in 2.5D and 3D ICs than there is to lose. At last week’s European 3D TSV Summit (January 21-22), two European manufacturers took to the podium to shared their reasons for implementing 2.5D and 3D in... »

3D NAND Flash – Towering Spires or Costly Canyons? – Part 4

3D NAND Flash – Towering Spires or Costly Canyons? – Part 4

If you’ve followed me thus far in the three preceding posts, well done! We started by questioning the cost assumptions. Then we set the scene to be able to explain the vanishing string current problem, and then introduced the concept of pass disturb. In this post, as promised in the previous one, I want to deal with pass disturb in more detail, which is one of the more important reliability chal... »

Part 2: 3D NAND Flash: Towering Spires or Costly Canyons?

Part 2: 3D NAND Flash: Towering Spires or Costly Canyons?

In my last blog posting I went over the cost aspects of the Samsung-Toshiba 3D NAND approaches. The conclusion is quite stark: if those vertical holes and trenches are more than a few tenths of a degree from the vertical, then the whole approach can be undercut in cost by more lithography-intensive layered approaches. At the risk of belaboring that point, see the IEEE paper published this month. N... »

Internet of Things

Friday’s Blog is brought to you by the Internet of Things

The Internet of Things, or “IoT” certainly seems to be the social media buzz phrase of the week. It seems every link I clicked on today took me to a post discussing the IoT. You can blame the flurry of technical blog coverage on recent events like the Trillion Sensors Summit, ARM TechCon 2013, CIsco’s Internet of Things World Forum, and Intel’s IDF 2013. All at once, Cisco Systems, Fai... »

Image Courtesy of TSMC Ltd.

What Node Names Really Mean; The TB/DB Saga continues; HMC update

Did you know that when foundries talk about 14nm and 16nm node chips, these devices are in reality no denser than their 20nm predecessors? Or that a particular node name does not reflect the size of any particular chip feature, as it once did? Or that since 2007, the doubling of transistors on a chip has actually been more like 1.6x the number of the previous generation? According to a recent feat... »

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