Devices

3D TSV Summiit

European 3D TSV Summit: But Wait, There’s More!

Day Two of the European 3D TSV Summit dawned bright and clear, with such a spectacular view of the nearby French Alps that it took real commitment to stay indoors and focus on the task at hand. But I have to admit that for the most part, it was worth the sacrifice to hear what this collection of speakers had to say. Georg Kimmich, head of Silicon Packaging R&D at ST-Ericsson delivered a dose o... »

MonolithIC 3D's PDN concept f removing heat from 3D ICs.

Tying up 2012 3D IC Loose Ends

I don’t know about you, but I always find that amidst the holiday hubbub, the really important stuff gets shoved aside and falls through the cracks. Just in case you missed them, here are some good 3D related posts that may have been lost in the December race to “get it all done” so we could enjoy the holidays. On the topic of the 3D IC supply chain, SemiMD’s Mark LePedus wrote a comprehen... »

The Other 3D: IEDM 2012 Zeroes in on 3D Memory and 3D Transistors

The Other 3D: IEDM 2012 Zeroes in on 3D Memory and 3D Transistors

Previews of IEDM 2012, which got underway today in San Francisco, indicate a program this year rich in content on 3D transistors and 3D memory technologies, with very little focus on 3D ICs using TSVs. My take on this is that IEDM papers are generally focuses on processes and technologies in early development. So while there was a lot to talk about in past years, 3D TSV technologies have matured p... »

3D Company Updates

3D Company Updates

There are a couple of notable updates circulating this week involving companies in the 3D space. The first I saw was news from Sony that it has introduced its next-generation CMOS Image sensor they claim is “ the industry’s smallest, CMOS image sensor and camera system”. The image sensor is a system-on-chip stacked structure featuring backside illumination (BSI). This is exciting progres... »

3D TSVs: Will Europe Lead the Way?

The first European 3D TSV Summit (January 22-23, 2013) hasn’t even happened yet, and already its intended message is becoming clear: Europe is ready to tackle those remaining issues and lead the world down the home stretch. It makes sense, since Europe’s R&D centers (imec, CEA Leti, Fraunhofer IZM) has been leading the way from the beginning, its foundries and IDMs (ST Microelectronics an... »

2.5D and 3D FPGA Update

Ever since TSMCs Open Innovation Platform (OIP) event, we’ve been hearing all about how the company has qualified its 2.5D chip-on-wafer-on-substrate (CoWoS) process flow, announced its test vehicle, and has begun shipping products. Indeed, at Roadmaps for Multi-die Packaging (November 14, 2012) Jan Vardaman used Altera’s adoption of the CoWoS test vehicle and design guidelines as an example ... »

3D IC Blogosphere Update

After wrapping up a run of blog posts from two weeks of travel and 4 conferences,(IWLPC 2012, the IEEE 3D Test Workshop, and MEPTEC’s co-located Roadmaps to Multi-die Integration and Known Good Die Symposium) it’s time to catch my breath and see what else has been going on in the 3D blogosphere. From the looks of Phil Garrou’s SST post, I missed out on hanging with “many of the world's 3... »

Multi-Die Integration Provides Multifaceted Solutions

Multi-Die Integration Provides Multifaceted Solutions By Francoise von Trapp, 3D InCites  This year’s Roadmaps for Multi-Die Integration Symposium, hosted by MEPTEC on November 14, 2012 at the Biltmore Hotel in Santa Clara, CA, offered some interesting and different perspectives than the garden-variety 2.5D and 3D IC conferences of late. While there were a number of process-focused presentati... »

What 3D Means in eWLB

Last week (November 6) STATS ChipPAC issued a press release announcing that its advanced eWLB provides a platform for 2.5D and 3D technologies.  In search of further information about this, I found a feature article recently published in Solid State Technology that explained how eWLB can be leveraged for 2.5D and 3D packages. I still had a few questions how it all works, and had the opportunity ... »

3D Technology Features in Review

The latest digital issues of Chip Scale Review and  iMicronews’ 3D Packaging magazines hit the virtual “stands” last week, and perhaps in honor if the 3D ASIP Conference that gets underway later this week, there are some hot new 3D technologies being featured. But first, to bring everyone up to speed, Jan Vardaman and Linda Mathew, TechSearch International, co-authored an editorial titled ... »

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