I spent this whole week at IMAPS 2012 in San Diego, and tweeted live from the event. Sometimes in the Twitter world, it’s difficult to extract full meaning from 140 character tweets, especially when they’re full of hashtags and @othertwitterhandles. And sometimes, we read them and ask, what was the point of that tweet? I thought it would be a fun exercise to decipher my own tweets for you, in order of appearance on my Twitter feed, and expand the information. And voila – my very first “tweeture!.”

Great chat with #Qualcomm’s Sam Gu about a PoP-like business model for wide I/0 DRAM on logic. Sam won best written paper at #IMAPS.
This tweet references my interview with Sam Gu following his presentation Tuesday morning, 3D Integration of Wide I/O Memory Cube Stacking to 28nm Logic Chip with High Density TSV Through a Fabless Supplier Chain, and is further discussed here in my blog post, Solving Wireless Challenges at IMAPS. One question I posed in the interview that I didn’t mention in the previous post, was Gu’s (and Qualcomm’s) perspective on TSMCs end-to-end offering for 3D ICs. Gu explained that while this scenario may work for TSMC, it doesn’t really work for Qualcomm. He explained that volume is too high to procure logic die from one foundry, and that it would be impossible to ship other company’s wafers to TSMC for assembly. Additionally, a foundry’s profit margin is higher than an OSAT, so it may be more cost effective to handle chipset assembly at the OSATS.

Come by the Lord booth to claim your cookie! #IMAPS @LORDelectronics This tweet was accompanied by an image similar to the one below. Lord Corporation sponsored a coffee break and supplied the cookies, but there seemed to be some confusion regarding the local for the break: Exhibit Hall or outside the Session area. I was just trying to help them out by sharing where their cookies could be found.


 Matt Grob of @Qualcomm is talking about device to device communication using LTE-Direct for improved proximal communication at #IMAPS
I expanded on this Tuesday keynote also in my aforementioned post, Solving Wireless Challenges at IMAPS. There’s also a cool movie that explains it halfway down the page. Check it out.

@SET-NA has their M&M’s out as usual at their #IMAPS booth!
Once again, this tweet was accompanied by the image below. Just trying to help a friend get some booth traffic. SET-NA is known for their peanut M&Ms.


SET-NA’s big news at the show was its new atmospheric plasma system that removes oxides from a wafer surface and passivates it at the same time so that it doesn’t re-oxidize. An unexpected bonus with this innovative technology is that it cleans, protects, and attracts the ability to bond for chip-to-chip, chip-to-wafer, or wafer-to-wafer production bonds.  Developed originally for Indium, it reportedly works well for a variety of metals, and is expected to help increase throughput by replacing process steps and chemistries such as flux or bond adhesives. The first system has been installed at a customer site. I hope to hear more about this going forward.

Unfortunately the WiFi at #IMAPS is spotty at best. Tweeting from my phone, but power is low. Real posts may take a few days! #3DInCites
General frustration was setting it at this point. I was burning up my phone battery tweeting using 3G. Luckily it gave me a way to at least stay connected and build up a great tweeture opportunity.

The new #3DInCites logo made it on the #IMAPS Media Sponsor poster! Snaps for #IMAPS!
Really, just a bit of shameless self-promotion.


Brad Eaton @AppliedMaterials deftly countered the notion that scallops Inherent to the Bosch process at #IMAPS. Zero scallop is possible.
I interview Brad Eaton, of Applied Materials, about his presentation Tuesday morning titled, The Truth about Scallops and Cost of Deep Silicon Etch.  I missed the presentation because I was traveling Tuesday morning, but Brad was kind enough to recap it for me. It had been recently publicized that scalloping resulting from the Bosch process for etching TSVs can lead to reliability issues, and current leakage. Eaton explained this is only in reference to scallops larger than those specified by industry standards. He explained that single step etch (the alternative to the Bosch process) is fine for low aspect ratio vias, such as those used for image sensors, but due to its inherent taper, isn’t suitable for high aspect ratio vias. His overall message: a certain amount of scalloping doesn’t affect reliability, however zero scallop can be achieved using the Bosch process with a minor throughput trade-off.

Michael Newman of @Invensas talked about #interconnectology, addressing #chokepoints, #2.5D processes leveraging legacy equipment; at #IMAPS
A lot to fit into 140 characters, I know.To be more succinct, Newman gave an overview of 2.5D and 3D technologies, noting that it’s not critical to decide which comes first; and that the goal is to interconnect chips with a high number of interconnects at lowest latency. He said 2.5D is less disruptive to adopt than 3D; and that in theory, its possible to drop in off-the-shelf die on silicon interposers, connect them and get latency improvements (although admittedly, not has high a performance improvement as in achieved in a custom designed 2.5D device). Additionally, 2.5D processing can leverage legacy equipment for some process steps, while high aspect ratio vias will require new, optimized 3D processes and equipment. Invensas is  working to clear “chokepoints” such as via fill, barrier, seed, alternatives to thin wafer handling, and cost. “Rather than putting band-aids on the problems, lets fix the problems,” said Newman. “Let’s not make it incrementally better, lets solve the issues at those chokepoints.”

That’s it for part one. Look for part 2 comprising tweets from 3D Thursday’s keynotes and panel discussion on Monday!  ~ F.v.T.

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