brought to you by:
For single die packages, electrostatic discharge (ESD) is well understood, and precautions are taken to minimize the possibility of charge build-up and ESD strikes. In single die designs, Input-Output (I/O) cells contain robust ESD protection circuitry. Additionally, ESD precautions are considered throughout the design, development, fabrication, and assembly/test of devices. As we move toward more... »
Being able to look inside an object without opening it up or destroying it, and separating the different features within that would otherwise overlap each other when seen in a standard 2D X-ray image, are the same for the needs of electronics inspection on wafers and on printed circuit boards, as they are in the medical sphere. If there is a problem on a wafer (or a person!) ideally we want to ana... »
High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. In June 2015, AMD introduced its Fiji processor, the first HBM 2.5D design, which comprises ... »
Frontier Semiconductor has recently introduced Virtual Interface Technology (VITTM) for TSV Inspection. In the realm of 2.5D/3D packaging, a high throughput/production ready metrology tool with a single high-performance sensor that addresses multiple measurement needs throughout the process flow, from FEOL to BEOL, can be very valuable in terms of yield improvement, cost of ownership reduction and... »
By: Ehab Mohsen, Xilinx To address the insatiable demand for bandwidth, the communications industry is accelerating development of Nx100G line cards for networking systems. In order for equipment manufacturers to scale infrastructure economically and effectively, they must leverage the latest optical interconnect technologies, suh as CFP2 and in the future CFP4, to increase bandwidth while lowerin... »
A memory stack on logic 3D TSS stack was considered for comparative study of warpage response to two different process choices, namely, Die to Die (D2D) and Package to Die (P2D) assembly. Process and reliability modeling software CielMech, and Commercial Finite Element Analysis (FEA) software ANSYS Mechanical were utilized to simulate thermo-mechanical effects of sequential chip attach, underfilli... »
By Dusan Petranovic, Member, IEEE, and, Karen Chow, Member, IEEE, (Mentor Graphics) The three largest EDA companies are taking an evolutionary, rather than a revolutionary, approach in developing the 3D IC design tools. This appears to be a good decision because the technology, the rules and the standards are still evolving. The main EDA challenges are expected in the design space exploration [6]... »
By Terry Bowen and Richard Miller, TE Connectivity The increasing transmission speeds in network switching, data storage, and super computing equipment makes it more and more difficult to use traditional electrical interconnects. Fiber optic links are a natural solution to this problem. Moving the optical fiber inside the box will demand smaller physical size modules that accommodate the increased... »
3D integration is being touted as the next semiconductor revolution by industry. 3D integration involves the use of various interconnects that include balls, pillars, bond wires, through silicon vias (TSV) and redistribution layers (RDL) for enabling chip stacking, interposer and printed circuit board (PCB) based technologies. More recently 2.5D integration using silicon interposers has gained mom... »
Over the last several years, the buzzword in the electronics industry has been “More than Moore”, referring to the embedding of components in the the package substrate and stacking of ICs and packages using wire bond and package-on-package (PoP) technologies. This has led to the development of technologies that can lead to ultra-miniaturization of electronic systems with coining of ter... »
Site Design By
Recent Comments