White Papers

Package Designers Need Assembly-level LVS Signoff for HDAP Verification

Package Designers Need Assembly-level LVS Signoff for HDAP Verification

While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced layout vs. schematic (LVS)-like verification techniques that can move across the entire package to ensure proper co... »

Optimizing Your SoCs and ASICs to Design PCBs More Cost Effectively

Optimizing Your SoCs and ASICs to Design PCBs More Cost Effectively

Many high-performance systems today use custom ASICs or SoCs to provide the necessary computational power and data bandwidth demanded by their host system, whether it’s a network storage device, network data switch, complex industrial equipment controller, or a critical core module of a defense system. And they are not getting any smaller or slower as silicon process nodes shrink and memory dema... »

Implementing High-Density Advanced Packaging for OSATs and Foundries

Implementing High-Density Advanced Packaging for OSATs and Foundries

Moore’s law is increasingly difficult to maintain and is driving the growth of innovative high-density advanced packaging (HDAP) technologies in response to system scaling demands. These innovations are increasingly in the form of fan-out wafer level packaging (FOWLP) or multi-substrate / multi-device packages like interposers and system-in-package (SiP). New challenges come with these disruptiv... »

Designing and Integrating MCM/SIP Packages into Systems PCBs

Designing and Integrating MCM/SIP Packages into Systems PCBs

Traditionally, MCMs (Multi-Chip-Modules) were a way of integrating several ASICs, or ASICs and memory, into a lower-cost, smaller form-factor, robust module that was an alternative to a single large SoC. Instead of integrating all or most of the systems PCBs needs onto a large and complex single SOC, you could design and fabricate smaller, high-yielding ASICs (Figure 1) and make them behave like a... »

Using Co-Design to Ensure Multi-Fabric System-Design Success

Using Co-Design to Ensure Multi-Fabric System-Design Success

Today’s SoCs, multi-core CPUs and GPUs with their high performance, high bandwidth interconnect interfaces put demanding challenges across the entire system signal path, requiring system-wide optimization for product success. However, although typical system substrate design discipline (chip, packaging, and PCB) have well-developed design approaches, the interaction between them largely remains ... »

Electromagnetic Simulation for Electronic Systems

Electromagnetic Simulation for Electronic Systems

Packages and boards are playing an increasing role as a way to increase speed and density while reducing power and form factor of electronic systems. This is part of a trend called sometimes “more than Moore”, to refer to factors in addition to scaling ICs. Packages and boards both represent sizeable industries, even compared to the $300 billion semiconductor industry. Packaging is estimated t... »

Electromagnetic Modeling of Three-dimensional Integrated Circuits

Electromagnetic Modeling of Three-dimensional Integrated Circuits

Three-dimensional Integrated circuits (3DIC) are generating increased interest as a way to increase speed and density while reducing power and form factor. System level integration in Package (SiP) has joined “System on Chip (SoC)” as one of the primary mechanisms to drive the electronics industry. Quotes such as “Smartphones and Tablets will increasingly owe their prowess to better chip pac... »

Implementing Fan-Out Wafer-Level Packaging (FOWLP) with an HDAP Flow

Implementing Fan-Out Wafer-Level Packaging (FOWLP) with an HDAP Flow

Fan-out wafer-level packaging (FOWLP) is an emerging type of high-density advanced packaging (HDAP) technology in the semiconductor industry that is rapidly gaining popularity in the market. But what exactly is FOWLP? Why do we need it? How do we take advantage of it? What limitations still need to be overcome? FOWLP brings single and multi-die designs together, combining multiple die from heterog... »

Solving the Design and Verification Challenges of High Density Advanced Packaging

Solving the Design and Verification Challenges of High Density Advanced Packaging

Today’s electronic products present new challenges to product development teams. As a result, there is a constant push to improve product quality and design efficiency through the use of new design technologies. For example, system-scaling demands change as Moore’s law becomes increasingly difficult to maintain, thus driving growth of innovative PCB and packaging technologies such as: High-den... »

High Productivity UBM/RDL Deposition by PVD for FOWLP Applications

High Productivity UBM/RDL Deposition by PVD for FOWLP Applications

Fan-out wafer level packaging (FOWLP) technology is an increasingly popular solution for obtaining high levels of device integration with a greater number of I/O contacts, at a lower cost. With FOWLP today we have the ability to embed heterogeneous devices including baseband processors, RF transceivers, and power management ICs in mold wafers, thereby enabling the latest generation of ultra-thin w... »

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