Eutectic Die Attach Optimizes High Power GaN Devices
Sep 09, 2020 · By StratEdge · Resource Library, White Papers
Latest Posts
The Implications of doing Business with Huawei
Summary: The United States Commerce Department is in the process of updating regulations on semiconductor trade with China. While over...
Optimizing Your SoC or ASIC to Design PCBs More Cost Effectively
Shrinking silicon process nodes and increasing memory demands are a nightmare for PCB design teams working with custom ASICs or...
Implementing High-Density Advanced Packaging for OSATs and Foundries
Moore’s law is increasingly difficult to maintain and is driving the growth of innovative, high-density advanced packaging technologies in response... Designing and Integrating MCM/SIP Packages into Systems PCBs
The challenge of designing smaller, cost-effective systems that require additional processing and performance power led to 3D chip stacking of... Using Co-Design to Ensure Multi-Fabric System-Design Success
As next-generation High-Density-Advanced-Packaging (HDAP) designs become more common, PCB designers and engineers are looking to system-level co-design to tie multi-substrate... Package Designers Need Assembly-level LVS Signoff for HDAP Verification
While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity... Optimizing Your SoCs and ASICs to Design PCBs More Cost Effectively
Many high-performance systems today use custom ASICs or SoCs to provide the necessary computational power and data bandwidth demanded by... Implementing High-Density Advanced Packaging for OSATs and Foundries
Moore’s law is increasingly difficult to maintain and is driving the growth of innovative high-density advanced packaging (HDAP) technologies in... Designing and Integrating MCM/SIP Packages into Systems PCBs
Traditionally, MCMs (Multi-Chip-Modules) were a way of integrating several ASICs, or ASICs and memory, into a lower-cost, smaller form-factor, robust... Using Co-Design to Ensure Multi-Fabric System-Design Success
Today’s SoCs, multi-core CPUs and GPUs with their high performance, high bandwidth interconnect interfaces put demanding challenges across the entire...
Electromagnetic Simulation for Electronic Systems
Packages and boards are playing an increasing role as a way to increase speed and density while reducing power and... Electromagnetic Modeling of Three-dimensional Integrated Circuits
Three-dimensional Integrated circuits (3DIC) are generating increased interest as a way to increase speed and density while reducing power and... Implementing Fan-Out Wafer-Level Packaging (FOWLP) with an HDAP Flow
Fan-out wafer-level packaging (FOWLP) is an emerging type of high-density advanced packaging (HDAP) technology in the semiconductor industry that is... Solving the Design and Verification Challenges of High Density Advanced Packaging
Today’s electronic products present new challenges to product development teams. As a result, there is a constant push to improve...
High Productivity UBM/RDL Deposition by PVD for FOWLP Applications
Fan-out wafer level packaging (FOWLP) technology is an increasingly popular solution for obtaining high levels of device integration with a...
Advancements in Carbon Nanostructures for Advanced Packaging Applications
Moore’s law has guided the continuing miniaturization and performance enhancements of silicon chips for the semiconductor industry by scaling the... Start Your 2.5D HBM Design Today
High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect...
The X-ray Metrology of TSVs and Wafer Bumps
Being able to look inside an object without opening it up or destroying it, and separating the different features within... ESD in 3D IC Packages
For single die packages, electrostatic discharge (ESD) is well understood, and precautions are taken to minimize the possibility of charge...