Moore’s law is increasingly difficult to maintain and is driving the growth of innovative, high-density advanced packaging technologies in response to system scaling demands. These innovations are increasingly in the form of fan-out wafer level packaging (FOWLP) or multi-substrate / multi-device packages like interposers and system-in-package (SiP).
New challenges come with these disruptive technologies as they employ silicon-like features and processes or multi-substrate architectures to facilitate high-performance memory devices like HBM/HMC.
Today’s high-density advanced packaging package design methodologies and tools are at an inflection point as significant as the transition from MCAD tools for lead frames to ECAD tools for PBGAs. The entry of silicon foundries into the packaging supply chain further disrupts tools and methodologies with their application of silicon PDKs (Process Design Kits) and verification processes to packaging.
HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabrication, and assembly predictability and package performance.