MentorPCB, Author at 3D InCites

Optimizing Your SoC or ASIC to Design PCBs More Cost Effectively

Optimizing Your SoC or ASIC to Design PCBs More Cost Effectively

Shrinking silicon process nodes and increasing memory demands are a nightmare for PCB design teams working with custom ASICs or SoCs on high-performance systems. Huge devices with challenging bump and package-ball net assignments must be integrated onto the PCB while overall system integrity is maintained and signal-layer count and overall PCB size stay within system and cost constraints. This pap... »

Implementing High-Density Advanced Packaging for OSATs and Foundries

Implementing High-Density Advanced Packaging for OSATs and Foundries

Moore’s law is increasingly difficult to maintain and is driving the growth of innovative, high-density advanced packaging technologies in response to system scaling demands. These innovations are increasingly in the form of fan-out wafer level packaging (FOWLP) or multi-substrate / multi-device packages like interposers and system-in-package (SiP). New challenges come with these disruptive tech... »

Designing and Integrating MCM/SIP Packages into Systems PCBs

Designing and Integrating MCM/SIP Packages into Systems PCBs

The challenge of designing smaller, cost-effective systems that require additional processing and performance power led to 3D chip stacking of bare die and a new approach to packaging known as SiP (systems-in-package), also known as multi-chip modules (MCMs). The benefits of MCM/SiP package technology include the ability to achieve greater functionality in a reduced time-to-market window that cann... »

Using Co-Design to Ensure Multi-Fabric System-Design Success

Using Co-Design to Ensure Multi-Fabric System-Design Success

As next-generation High-Density-Advanced-Packaging (HDAP) designs become more common, PCB designers and engineers are looking to system-level co-design to tie multi-substrate visualization, planning, and optimization, into a complete multi-board design. Co-design methodology allows design teams to plan and optimize I/O and connectivity from a chip, through multiple packaging scenarios, and on to p... »

Package Designers Need Assembly-level LVS Signoff for HDAP Verification

Package Designers Need Assembly-level LVS Signoff for HDAP Verification

While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced layout vs. schematic (LVS)-like verification techniques that can move across the entire package to ensure proper co... »

Optimizing Your SoCs and ASICs to Design PCBs More Cost Effectively

Optimizing Your SoCs and ASICs to Design PCBs More Cost Effectively

Many high-performance systems today use custom ASICs or SoCs to provide the necessary computational power and data bandwidth demanded by their host system, whether it’s a network storage device, network data switch, complex industrial equipment controller, or a critical core module of a defense system. And they are not getting any smaller or slower as silicon process nodes shrink and memory dema... »

Implementing High-Density Advanced Packaging for OSATs and Foundries

Implementing High-Density Advanced Packaging for OSATs and Foundries

Moore’s law is increasingly difficult to maintain and is driving the growth of innovative high-density advanced packaging (HDAP) technologies in response to system scaling demands. These innovations are increasingly in the form of fan-out wafer level packaging (FOWLP) or multi-substrate / multi-device packages like interposers and system-in-package (SiP). New challenges come with these disruptiv... »

Designing and Integrating MCM/SIP Packages into Systems PCBs

Designing and Integrating MCM/SIP Packages into Systems PCBs

Traditionally, MCMs (Multi-Chip-Modules) were a way of integrating several ASICs, or ASICs and memory, into a lower-cost, smaller form-factor, robust module that was an alternative to a single large SoC. Instead of integrating all or most of the systems PCBs needs onto a large and complex single SOC, you could design and fabricate smaller, high-yielding ASICs (Figure 1) and make them behave like a... »

Using Co-Design to Ensure Multi-Fabric System-Design Success

Using Co-Design to Ensure Multi-Fabric System-Design Success

Today’s SoCs, multi-core CPUs and GPUs with their high performance, high bandwidth interconnect interfaces put demanding challenges across the entire system signal path, requiring system-wide optimization for product success. However, although typical system substrate design discipline (chip, packaging, and PCB) have well-developed design approaches, the interaction between them largely remains ... »

Electromagnetic Simulation for Electronic Systems

Electromagnetic Simulation for Electronic Systems

Packages and boards are playing an increasing role as a way to increase speed and density while reducing power and form factor of electronic systems. This is part of a trend called sometimes “more than Moore”, to refer to factors in addition to scaling ICs. Packages and boards both represent sizeable industries, even compared to the $300 billion semiconductor industry. Packaging is estimated t... »

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