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Designing and Integrating MCM/SIP Packages into Systems PCBs

Designing and Integrating MCM/SIP Packages into Systems PCBs

The challenge of designing smaller, cost-effective systems that require additional processing and performance power led to 3D chip stacking of bare die and a new approach to packaging known as SiP (systems-in-package), also known as multi-chip modules (MCMs). The benefits of MCM/SiP package technology include the ability to achieve greater functionality in a reduced time-to-market window that cann... »

Using Co-Design to Ensure Multi-Fabric System-Design Success

Using Co-Design to Ensure Multi-Fabric System-Design Success

As next-generation High-Density-Advanced-Packaging (HDAP) designs become more common, PCB designers and engineers are looking to system-level co-design to tie multi-substrate visualization, planning, and optimization, into a complete multi-board design. Co-design methodology allows design teams to plan and optimize I/O and connectivity from a chip, through multiple packaging scenarios, and on to p... »

Package Designers Need Assembly-level LVS Signoff for HDAP Verification

Package Designers Need Assembly-level LVS Signoff for HDAP Verification

While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced layout vs. schematic (LVS)-like verification techniques that can move across the entire package to ensure proper co... »

Perspectives on the Cost of Fan-out Wafer Level Packaging vs. Flip Chip Packaging

Perspectives on the Cost of Fan-out Wafer Level Packaging vs. Flip Chip Packaging

Recently, I read a paper published in the 2017 IMAPS Device Packaging Conference proceedings, titled “Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging,” written by Amy Lujan, of Savansys. Lujan did a very good analysis on the cost comparison of fan-out wafer-level packaging (FOWLP)  with chip-first and die face-down and flip chip (FC) packaging, according to a... »

Striking the Right Chord for Chiplet Integration

Striking the Right Chord for Chiplet Integration

The growing digitalization of our society has made our lives connected and, in many aspects, easier. But the digital revolution also implies that the total amount of data processed in the world is doubling every two years or so. Electronic devices such as mobile phones, laptops, satellites, servers or self-driving vehicles must cope with twice as much data, at higher speeds. Traditional signaling ... »

Optimizing Your SoCs and ASICs to Design PCBs More Cost Effectively

Optimizing Your SoCs and ASICs to Design PCBs More Cost Effectively

Many high-performance systems today use custom ASICs or SoCs to provide the necessary computational power and data bandwidth demanded by their host system, whether it’s a network storage device, network data switch, complex industrial equipment controller, or a critical core module of a defense system. And they are not getting any smaller or slower as silicon process nodes shrink and memory dema... »

Implementing High-Density Advanced Packaging for OSATs and Foundries

Implementing High-Density Advanced Packaging for OSATs and Foundries

Moore’s law is increasingly difficult to maintain and is driving the growth of innovative high-density advanced packaging (HDAP) technologies in response to system scaling demands. These innovations are increasingly in the form of fan-out wafer level packaging (FOWLP) or multi-substrate / multi-device packages like interposers and system-in-package (SiP). New challenges come with these disruptiv... »

Concept for 3-dimensional stacking of Flash devices. A thin film field effect transistor with a silicon nitride as charge reservoir and a tunnel oxide. A.J. Walker et al., VLSI Symposium, 2003.

The Future of Non-volatile Memory

Part 4 of the series, The Triumph of Quantum Mechanics at the Heart of Solid-State Data Storage, continues with the future of non-volatile memory. The figure above is a concept for 3D stacking of Flash devices. A thin-film field effect transistor with a silicon nitride as charge reservoir and a tunnel oxide. A.J. Walker et al., VLSI Symposium, 2003. The relentless shrinking of NAND Flash from ... »

Designing and Integrating MCM/SIP Packages into Systems PCBs

Designing and Integrating MCM/SIP Packages into Systems PCBs

Traditionally, MCMs (Multi-Chip-Modules) were a way of integrating several ASICs, or ASICs and memory, into a lower-cost, smaller form-factor, robust module that was an alternative to a single large SoC. Instead of integrating all or most of the systems PCBs needs onto a large and complex single SOC, you could design and fabricate smaller, high-yielding ASICs (Figure 1) and make them behave like a... »

The Invention of NAND Flash Memory

The Invention of NAND Flash Memory

Part 3 of the series, The Triumph of Quantum Mechanics at the Heart of Solid-State Data Storage, continues with the invention of NAND flash memory. The above image is of the first comprehensive paper reporting the NAND Flash invention where Fowler-Nordheim tunneling is used for program and erase of the memory. [1] After the fundamental studies in the late 1960’s Quantum Mechanical tunneling... »

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