Book Review: Handbook of 3D Integration – Volume 4
Jun 11, 2019 · By Herb Reiter · Book Reviews, Resource Library
Latest Posts - Page 3
Advancements in Carbon Nanostructures for Advanced Packaging Applications
Moore’s law has guided the continuing miniaturization and performance enhancements of silicon chips for the semiconductor industry by scaling the... Challenges and Solutions for EDA of 3D Chip Stacks
It is often claimed that 3D chip stacks offer the potential to meet current and future requirements of digital circuits,... Start Your 2.5D HBM Design Today
High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect... Opportunities for 2.5D and 3D Cost Reduction
A little over a year ago, I wrote a Knowledge Portal entry about the cost of 3D ICs. Here I... Micro and Nano X-ray Tomography of 3D IC Stacks
Advanced packaging, and particularly 3D through silicon via (TSV) integration technologies and the resulting 3D-stacked products, challenge materials and process... Cost Analysis of a Wet Etch TSV Reveal Process
Through silicon via (TSV) technology is a key design element being incorporated into more and more advanced packaging designs today.... Fraunhofer EMFT: Our Early and Ongoing Work in 3D Integration
Fraunhofer has been working on 3D integration for the past three decades, starting in1987 with a consortium of Siemens, AEG, Philips...
The Commercialization of 3D Stackable Memory – Part Two
The Opportunities for RRAM Cells to Take 3D Stackable Memory to 8-nm Nodes In Part One of this two-part series,...
The Commercialization of 3D Stackable Memory: Part One
The Challenges of Manufacturing 3D Stackable Memory Memory technologies vying to fulfill the increasing capacity and density requirements of the...
TSV Technology Trends and Fabrication Details: A Short Course
3D/TSV technology has been the subject of intense development over the last 10-15 years. During this time, many process advancements...
Improving R&D Efficiency to get “Moore” out of Chips
The semiconductor industry invests more in R&D than any other industry except pharmaceuticals. At the same time, It is dealing... How 2.5/3D Technologies Will Shake Up the Semiconductor Supply Chain and Cost Structure
At the 2015 3D InCites Awards Breakfast, which took place July 16, 2015 at the Impress Lounge during SEMICON West,... Comparing Two Flavors of Chip Stacking Yield
One of the ways to build more complex, powerful, and cost-effective electronic systems is stacking chips on top of each... Wafer-to-Wafer Bonding Cost Analysis
Last year, I did an analysis that included the topic of wafer-to-wafer bonding. Specifically, it was a comparison of the... CoolCube™: A True 3DVLSI Alternative to Scaling
Stacking transistors on top of each other sequentially in the same front-end process flow is a concept that has been imagined... The X-ray Metrology of TSVs and Wafer Bumps
Being able to look inside an object without opening it up or destroying it, and separating the different features within... ESD in 3D IC Packages
For single die packages, electrostatic discharge (ESD) is well understood, and precautions are taken to minimize the possibility of charge... Technology Options and Their Influence on Routing for Interposer-based Memory Processor Integration
Currently in advanced integration, mainly stacked solutions (Figure 1b) are considered due to their attractive compactness. But if the ASIC... Understanding Heterogeneous 3D Integration
“How is heterogeneous 3D integration defined?” There are certainly different understandings in the microelectronics community regarding the definition of heterogenous... 