Fraunhofer has been working on 3D integration for the past three decades, starting in1987 with a consortium of Siemens, AEG, Philips and the Munich institute IFT (now EMFT).  By 1988, we could successfully fabricate 3D CMOS devices based on recrystallization of deposited poly-Si. In the mid-1990s, we developed a complete process flow for “Through-Si Via technology (TSV) in close cooperation with Siemens: The “InterChip Via Technology” [1, 2]. Very early, we pointed out thermal issues and presented thermal analysis of vertically integrated circuits [3], proposed memory on logic as a key application for 3D technology, and investigated the performance improvement of the memory hierarchy of RISC systems [4].

By the end of the 1990´s we focused on 3D technologies using known good dies (KGD) by chip-to-wafer stacking (against at the time´s main stream of wafer-to-wafer-stacking) in a large German project with Infineon and Giesecke & Devrient [5]. Understanding the necessity for combining research on both 3D technology and simulation and design at an early stage, we established a fruitful cooperation between the two Fraunhofer institutes in Munich and IIS-EAS Dresden.

In the European Integrated Project e-CUBES, we developed the first technology platform for 3D heterogeneous integration in a consortium with a. o. Infineon, Philips, Thales, SensoNor, 3D-Plus, IMEC, CEA-Leti and Fraunhofer. The target application for this joint platform was the fabrication of miniaturized MEMS/IC systems using 3D system-on-chip (3D-SoC) technologies [6]. In close cooperation with Infineon, we focused early on producibility and reliability issues of such heterogeneous 3D integrated systems, especially the impact of TSVs and wafer bonding processes on performance and reliability. Starting in 2010, within the European large-scale Integrating Project, e-BRAINS, a consortium of Infineon, Siemens, Sorin, 3D Plus, IMEC, CEA, SINTEF, Tyndall, Fraunhofer and others, heterogeneous 3D integrated system demonstrators in five key applications were fabricated and evaluated: Bio Sensors (Magna, Infineon), Infrared Imager (SensoNor, SINTEF), Active medical Implants (Sorin), Smart Gas Sensors (Siemens) and Ultrasound Imaging Probes (Vermon).

A particular focus of the e-BRAINS project was the development of novel, low-temperature processes for highly reliable, 3D integrated sensor systems [7]. As another key application, we demonstrated high-performance communication devices with Infineon Technologies Austria, IMEC, Fraunhofer and EPFL. For high-frequency components, Fraunhofer EMFT developed a specific fine-pitch 3D-TSV technology for RF-MEMS and RF-IC applications. High-performance RF test structures were designed and evaluated by EPFL and IMEC [8].

One of the main drivers of 3D heterogeneous integration is certainly sensor integration. The system integration of sensors with ICs, passive components and even energy harvesting systems is becoming more and more important, especially for the high growth market area of distributed wireless sensor systems, which will constitute the key connected hardware infrastructure of the Internet of Things (IoT). In consequence, our ongoing work has a dedicated focus on 3D TSV technologies for heterogeneous sensor/IC systems in future key application areas, as e.g. medical and health care devices. The European NMP project, MANpower is targeting a leadless pacemaker in a perpetually self-powered concept. Within the consortium of Tyndall, Sorin (now LivaNova), KU Leuven and others, Fraunhofer EMFT and 3D Plus are in charge of the 3D system integration for the electronic sub-component, consisting of ICs, MEMS and passives, interconnected and assembled with the energy harvesting system in a highly miniaturized implantable capsule.

For more information about the early and ongoing work in 3D integration, download the presentation: Early and Ongoing Work in 3D Integration.

[1] T. Grassl, P. Ramm, M. Engelhardt, Z. Gabric, O. Spindler, First International Dielectrics for VLSI/ULSI Interconnection Metallization Conference – DUMIC, Santa Clara, CA, 20-22 Feb, 1995
[2] P. Ramm et al, Microelectronic Engineering 37/38 (1997), pp. 39-47
[3] M.B. Kleiner, S.A. Kuehn, P. Ramm, W. Weber, IEDM Tech. Digest (1995)
[4] M.B. Kleiner, S.A. Kuehn, P. Ramm, W. Weber, IEEE Transactions on Components, Packaging, and Manufacturing Technology – Part B, Vol. 19, No. 4 (1996)
[5] P. Ramm, A. Klumpp, R. Merkel, Josef Weber, R. Wieland, G. Elst, Proc. Solid State Devices and Materials – SSDM 2003, Tokyo and Japanese Journal of Applied Physics 43 (7A), L 829 (2004)
[6] P. Ramm, A. Klumpp, J. Weber, M.M.V. Taklo, Microsystem technologies 16 (2010), pp. 1051-1055
[7] P. Ramm, A. Klumpp, J. Weber, A. Mathewson, K.M. Razeeb, R. Pufall, Proc. IMAPS Device Packaging Conference, Scottsdale, AZ, 16-19 March, 2015
[8] W.A. Vitale, M. Fernandez-Bolanos, R. Merkel, A. Enayati, I. Ocket, W. de Raedt, J. Weber, P. Ramm, A.M. Ionescu, Proc. 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, 26-29 May, 2015, pp. 585-590, DOI: 10.1109/ECTC.2015

Peter Ramm

Dr. Peter Ramm is responsible for the key competence “Si Processes, Device and 3D Integration”.…

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