Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging
In recent years, there has been an increased focus on fan-out wafer level packaging. While fan-out wafer level packaging may be the right solution for some designs, it is not always the lowest cost solution. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. Both technologies are suitable for many of the same applications, and it is important to understand the cost drivers of both fan-out wafer level packaging and flip chip packaging that result in one being more cost-effective over the other.
The process flows for both technologies are introduced briefly to frame the comparison.
Flip Chip Packaging
The flip chip process begins with the fabrication of a substrate and then die with bumps or copper pillars are assembled onto the substrate. The key activities for a typical flip chip process are outlined in Figure 1, though process variations may exist (e.g. molded underfill versus capillary underfill plus overmold). Key flip chip cost drivers are package size, substrate structure, and the cost of bumping the incoming wafer.
Note that there are three points in the flip chip processing flow where the die or package may be scrapped.
Fan-out Wafer Level Packaging
There are a few varieties of fan-out wafer level packaging on the market. The version analyzed in this comparison is a die-first face-down process, outlined in tFigure 2. Unlike the flip chip process, there are not separate substrate and assembly portions of the fan-out process. The incoming semiconductor wafer is diced but not bumped, and the substrate is essentially formed around the die. Key cost drivers are package size, the number of imaging steps (depends on the number of RDLs), and yield.
In contrast to the flip chip flow, there are only two points during the fan-out WLP process when the die or package may be scrapped.
Activity based cost modeling was used to construct generic flip chip and die-first face-down fan-out wafer level packaging models. With activity-based cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is calculated. The cost of each activity is determined by analyzing the following attributes: time required, the amount of labor required, the cost of material required (consumable and permanent), tooling cost, all capital costs, and yield loss associated with the activity.
There are many factors that impact the cost of a design. Some of the most basic design details are the package size, die size, the number of I/Os, and substrate structure. To carry out a meaningful cost comparison between these two technologies, a variety of comparisons are carried out to isolate individual variables. By isolating single design features, trends that favor one package type over another can be seen.
One caveat for this approach is that most real-world examples would involve numerous design details changing between the two technologies, such as a fan-out package being smaller than its complementary flip chip package. Therefore, this analysis points out trends that support one technology over the other, but trade-offs still need to be carried out to understand specific design comparisons.
Finally, note that a flip chip package with a 1-2-1 substrate is included in the graphs as a point of reference, but the discussion will focus on the crossover point between fan-out packaging with a single RDL and a flip chip package with a 2L substrate.
Varying Package Size
The first set of data compares the cost when packaging the same die in different package sizes. I/O count is also adjusted accordingly. The charts in Figure 2 show only the processing costs for both packaging types. Neither the cost of the die or the loss of any die, are included.
For the larger die, the crossover point happens around the 9x9mm package, which is when fan-out wafer level packaging stops being cost-efficient. With the smaller die, this crossover point happens earlier, around the 6.5×6.5mm package size.
The takeaway is that the larger the package size, the more likely flip chip processing will become cost-effective. However, the package size at which this occurs will depend on the design. The size of the package itself is less important than the size of the package in relation to the die. For fan-out processing, the smaller the package in relation to the die, the less mold required. This results in lower processing costs.
As seen by the sharp slope, fan-out WLP is very sensitive to package size. This is because the majority of the activities are performed on the entire wafer at once, resulting in a per wafer cost for an activity, not a per package cost. As the package size is increased, that per wafer cost is amortized over a smaller number of packages.
Varying Die Size
The next analysis keeps the package size constant while the size of the die being packaged changes (Figure 3). In these examples, the cost of the die (and scrapping that die) is included.
First, note how the cost of the fan-out wafer level package is nearly static, with the cost going down at the larger die sizes, since larger die reduce the amount of mold required. On the other hand, the cost of the flip chip package changes with die size even though the package size is static because a larger die brings in a higher processing (bumping) cost. The cost of bumping is not insignificant.
When only processing costs are taken into account, the crossover point between FOWLP and the FC 2L package is close to the 7.5×7.5mm die scenario. With a one-dollar die, the crossover is pushed to the 8.5×8.5mm die scenario; with a two dollar die, the crossover happens with a 9x9mm die. This illustrates that the fact that the more expensive the die being packaged, the higher the potential scrap cost of fan-out packaging. This increased scrap potential results in flip chip packaging being cost-effective for more scenarios as more expensive die are evaluated. This is due to the differing number of scrap points in the process flows.
Since the loss of die due to defects in the fan-out process is a key factor when comparing these two technologies, this section analyzes the impact of yield in more detail. These cost models use defect density assumptions for particular activities in the process flows. Defect density is the probability that a defect will occur in a 1cm2 area. The models assume that one defect anywhere within the package area will cause that package to be scrapped.
The following charts repeat the two previous examples, but the defect density for the fan-out process is adjusted across a range (Figure 4). The legend refers to additional defect density added in each fan-out case. Since most people think in terms of process yield rather than defects per square centimeter, it should be noted that the 0.02 line corresponds to a ~99% process yield for the 7x7mm package. The 0.04 line is comparable to ~98% process yield. The yield of the flip chip process is also in the high nineties.
It’s worth noting that current fan-out processes support a yield that is generally higher than 99%. This evaluation was carried out to characterize the impact of yield, however, not to describe current yield trade-offs for simple packages. More complex fan-out WLP packages and newer technologies will have more yield issues to consider, which is why understanding the impact of yield is important.
In the one dollar die example above, the flip chip package is more expensive than the fan-out package with the best yield until the 6x6mm package mark. When compared to the fan-out package with the lowest yield, this crossover happens around the 5x5mm package. In the two-dollar die example, the fan-out scenario with the best yield is more cost-effective until a 7.5×7.5mm package, while the fan-out scenario with the worst yield is more cost-effective only up to a 5x5mm package size. The key conclusions drawn earlier — that flip chip packages are more likely to be cost-effective at higher package sizes, and that more expensive die reduce the cost-effectiveness of fan-out—are reinforced by this yield analysis.
The above charts hold the package size at 13x13mm and vary the die size (Figure 5). When a one dollar die is considered, the highest yield fan-out package is cost-effective in all but the first two scenarios. The lowest yield fan-out package is only cost-effective beginning at an 8.5×8.5mm die size. For the two-dollar die, the highest yield fan-out package is cost-effective starting at a 7x7mm die, and the lowest yield fan-out package is more cost-effective starting at a 10x10mm die. The key takeaway here is to remember that the fan-out WLP costs are barely impacted by die size, which means the way the crossover points shift is purely based on the impact of yield.
The cost of flip chip packaging is sensitive to package size, substrate structure, and the cost of bumping the incoming wafer. Fan-out wafer level packaging is sensitive to package size, the number of redistribution layers, and yield.
Initial analysis showed that flip chip packaging is more likely to be cost-effective at larger package sizes, though the point at which it becomes cost-effective depends on the design details. On the other hand, the cost to bump the die that will be placed in a flip chip package is a primary reason that flip chip packaging can be more expensive than fan-out wafer level packaging.
Fan-out wafer level packaging has fewer scrap opportunities than flip chip, which makes fan-out processing more sensitive to yield changes. Different defect density assumptions were used to illustrate how the crossover point between fan-out and flip chip packaging costs shifts depending on the yield of the fan-out process. It was also shown that the more expensive the die being packaged, the more likely flip chip package will be cost-effective.