FOWLP

IFTLE 398: Samsung’s 256Gb 3DS (TSV-Stacked) RDIMM; IMAPS 2018 in Pasadena

IFTLE 398: Samsung’s 256Gb 3DS (TSV-Stacked) RDIMM; IMAPS 2018 in Pasadena

Samsung at the Leading Edge At the recent Samsung Tech Day, the company unveiled several new technologies: Their 7nm extreme ultraviolet (EUV) process node from Samsung’s foundry business SmartSSD – a field programmable gate array (FPGA) SSD, that will offer accelerated data processing and the ability to bypass server CPU limits QLC-SSD for enterprise and data centers that offer 33%t more... »

Talking Nerdy with Exhibitors at IWLPC 2018

Talking Nerdy with Exhibitors at IWLPC 2018

With heterogeneous integration, 3D, and advanced wafer-level packaging technologies officially declared the rising stars of the semiconductor industry, materials, process and equipment suppliers have pulled out their shiniest bells and whistles. Here’s a sampling of news and products that were on display at IWLCP 2018, October 23-25, 2018 at the Doubletree Hotel in San Jose. Indium Corporation... »

Bridging the Interconnect Pitch Gap Calls for 3D Technologies

Bridging the Interconnect Pitch Gap Calls for 3D Technologies

Last week at IWLPC, keynote speaker, Doug Yu, TSMC, kicked off the event with a similar storyline used by ASE’s Tien Wu during his IMAPS Symposium keynote earlier this month: High-performance applications like artificial intelligence (AI), 5G, autonomous driving, and even high-end smartphones are driving the continuation of Moore’s Law augmented by More than Moore. This need for high-performan... »

Perspectives on the Cost of Fan-out Wafer Level Packaging vs. Flip Chip Packaging

Perspectives on the Cost of Fan-out Wafer Level Packaging vs. Flip Chip Packaging

Recently, I read a paper published in the 2017 IMAPS Device Packaging Conference proceedings, titled “Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging,” written by Amy Lujan, of Savansys. Lujan did a very good analysis on the cost comparison of fan-out wafer-level packaging (FOWLP)  with chip-first and die face-down and flip chip (FC) packaging, according to a... »

Transforming the Fan-out Landscape

Transforming the Fan-out Landscape

These days, the first thing that comes to mind when someone mentions fan-out (FO) technology is Apple’s A10 processor built on TSMCs integrated fan-out (InFO) technology. It’s the superstar application that put FO on the map and into high volume manufacturing. However, equally important to remember are the numerous low-density FO workhorses supporting other mobile applications, as well as mark... »

TechSearch International Analyzes Trends in FO-WLP including Panel Activity

TechSearch International Analyzes Trends in FO-WLP including Panel Activity

While Apple remains the main customer for TSMC’s Integrated Fan-Out WLP (InFO-WLP), an increasing number of companies are adopting a large area version of FO on Substrate. HiSilicon has been in production with ASE’s FOCoS for several years and MediaTek just announced a logic device for networking applications using TSMC’s InFO on Substrate (InFO_oS). TSMC’s FO-WLP platform has been extende... »

There’s a Fan-out for That

There’s a Fan-out for That

Long gone are the days of the “killer app” and the notion that a single device market like personal computers (PCs) or smartphones alone can make or break the semiconductor industry. In fact, while both those markets have softened, a multitude of emerging technologies including 5G, artificial intelligence (AI), internet of things (IoT) platforms, deep learning, autonomous vehicles, blockchain ... »

Advanced Packaging Trends – Part II: Solving Lithography Challenges

Advanced Packaging Trends – Part II: Solving Lithography Challenges

Part 1 of this advanced packaging (AP) article series focused on solving photoresist (PR) strip and under bump metallization (UBM) / redistribution layer (RDL) challenges. This article looks at AP trends from a lithography standpoint and proposes solutions to associated lithography challenges. The need for advanced packaging solutions is greater than ever as the world continues to demand increased... »

Citius, Altius, Fortius Redux: More From SEMICON Korea 2018

Citius, Altius, Fortius Redux: More From SEMICON Korea 2018

The Winter Games are over and the athletes returned home, and the SEMICON Korea 2018 teams from February have their sights on SEMICON China this month after all that snow-in-Seoul settled, but I still have a few more comments about the Electropackage System and Interconnect Product technical session SEMI organized for the afternoon of 01 February 2018, and on which I reported in my first installme... »

Panel Level Packaging: The Next Sleeping Giant? And Other Thoughts From IWLPC 2017

Panel Level Packaging: The Next Sleeping Giant? And Other Thoughts From IWLPC 2017

To the best of my recollection (and a quick search through 3D InCites’ archives) the panel level packaging (PLP) hoopla first hit the conference circuit in 2015 at the International Wafer Level Packaging Conference (IWLPC), when Jan Vardaman made it the topic of a panel discussion, and told a cautionary tale of following PLP down the rabbit hole. It seems that ever since, PLP has been an event h... »

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