This year’s SEMI 3D & Systems Summit was held in late January in Dresden. In the next few blogs, we will take a look at some of the interesting material that was presented.

Savansys Activity-based Cost Modeling

Amy Lujan from Savansys discussed their activity-based cost modeling of a chip on interposer on substrate packaging solutions, like TSMC’s CoWoS.

Four high bandwidth memory (HBM) stacks and a 19 x 25mm logic die are assembled onto a 33 x 27 silicon interposer. Die to interposer connections are done through three layers of dual-damascene redistribution layer (RDL) processing performed in the fab’s front-end-of-line (FEOL). The interposer to 45 x 45 BGA substrate is fabricated using Cu/polymer RDL. This assumes a 100% yield of chips and substrates being placed. The overall process flow used for cost modeling is shown below:

 

Cost by process segment is shown below:

cost modeling

THE DetailS on what’s involved with these segments is discussed below:

  • TSV Creation: photolithography to define the TSVs, DRIE to create the TSV, metallization to fill the TSV
  • Interposer Silicon: material cost of the Si wafer that becomes the interposer
  • Temp bond/Debond: self-evident
  • TSV Reveal: grinding and CMP used to reveal TSV from the backside
  • Back-end-of-line (BEOL) RDL: 10um L/S RDL for interposer to BGA
  • UBM: Imaging to form under bump metallization (UBM) on the bottom of the Interposer
  • Die to Interposer Assembly: die placed on the interposer, underfilled, over-molded, packages diced
  • Interposer to Substrate Assembly: assembled interposer placed un substrate, underfilled, solder ball placed on the substrate

They then compared this to a high-density, chips-last fan-out-wafer-level-package (FOWLP) on substrate packaging such as ASE Groups’ FoC0S solution. Their proposed process flow is:

cost modeling

They modeled a module with 2 HBM stacks and a 15X15mm logic die on a 30X25 fan-out structure. Die to interposer connections are formed through three layers of dual damascene RDL processing done by the OSAT. This structure is subsequently mounted on the 45X45 BGA substrate. Again, this assumes a 100% yield of chips and substrates being placed.

Cost by process segment is shown below:

cost modeling

 

Although it would be more interesting to compare the proposed final cost of manufacturing for these two examples, it is interesting that Savansys claims the RDL in both cases drives the overall cost.

IFTLE notes that this is a three-layer RDL connection in both cases, which for the silicon case would not be as impactful (or costly) if the module required only 1 layer of high-density (i.e. 1µm) RDL.  Certainly, in the chips-last fanout package the elimination of the silicon interposer materials cost, the TSV formation, and the TSV reveal steps will reduce cost vs the silicon interposer case, but again it would have been nice to have the modeled manufacturer costs to compare. Where is the cross over point if the silicon interposer uses 1 layer of <1µm RDL vs the fan-out package with lower density L/S and pad pitch? At the end, that’s what really counts…

For all the latest on Advanced Packaging stay linked to IFTLE………………………

 

 

Phil Garrou

Dr. Philip Garrou is a subject matter expert for DARPA and runs his consulting company…

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