IFTLE 440: Copper Pillar Bump Development for 7nm Node Devices
Feb 10, 2020 · By Phil Garrou · Blogs, Packaging IFTLE
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IFTLE 437: Packaging Trends for Artificial Intelligence
As it has in recent years, SEMICON Europa 2019 featured a dedicated Advanced Packaging Conference. In this and my next...
IFTLE 433: AMD Chiplets go Commercial Amidst a Need for Chiplet Standardization
In 2017, AMD used chiplets in their “Zen 2” architecture to develop the Epyc server processor “Naples” (Figure 1). AMD...IFTLE 432: Ferric and TSMC Partner on Voltage Regulators; High TC Die Attach for TIM?
The IMAPS International Symposium took place this year in Boston. Let’s take a look at a few of the more...
IFTLE 431: Samsung Qualifies EDA Tools for Multi-die Integration
Samsung reports that they have seen increasing interest in multi-die integration (what they call MDI) for markets such as artificial...
IFTLE 430: Exascale Computing in Europe: Leading Edge Packaging is the Key!
Beyond HPC High-performance computing (HPC) has become an important tool for areas that generate high volumes of data. While today’s...
IFTLE 429: Samsung 12-layer memory with 3D-TSV; SHIP Winners
Samsung Electronics has announced the development of 12-layer memory using 3D through silicon via (3D-TSV) chip packaging technology. TSVs vertically...
IFTLE 428: Panel Level Processing: We’ve Come A Long Way Baby!
It was in 1992 when Ted Tessier and I, in our paper, “Overview of MCM Technologies: MCM-D”, at the IMAPS...
IFTLE 427: TSMC’s Next-Gen 3D Technology – N3XT
Continuing our look out into the future, at the recent Hot Chips Conference, Dr. Phil Wong, VP of R&D at TSMC...
IFTLE 426: Exascale Computing is Near; Incandescent Lightbulbs get a Reprieve
Earlier this year, John Shalf, department head of Computer Science at Lawrence Berkeley National Labs (LBNL) presented a plenary presentation...