IFTLE 444: Chip on Interposer on Substrate vs High Density Chips-Last Package Cost Modeling
Mar 26, 2020 · By Phil Garrou · Blogs, Packaging IFTLE
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IFTLE 441: Will TSMC Ever Put a Chip or Packaging Facility in the USA?
While we are all conjuring visions of what advanced packaging and in fact transistors themselves will look like in the...
IFTLE 437: Packaging Trends for Artificial Intelligence
As it has in recent years, SEMICON Europa 2019 featured a dedicated Advanced Packaging Conference. In this and my next...
IFTLE 436: Fluxless µBumping; Latest on Stacking Technologies
The November Issue of Chip Scale Review contains some interesting advanced packaging information that is worthy of sharing in IFTLE:...
IFTLE 435: The Heterogeneous Integration Roadmap (HIR)
Before we start this week’s blog, let me take the opportunity to wish all IFTLE readers a Merry Christmas and...
IFTLE 434: Process Optimization for a Reliable NXP FOWLP Microcontroller
There are several different fan-out wafer-level packaging (FOWLP) technologies that are currently in high-volume production. The traditional fan-out (FO) technology...
IFTLE 433: AMD Chiplets go Commercial Amidst a Need for Chiplet Standardization
In 2017, AMD used chiplets in their “Zen 2” architecture to develop the Epyc server processor “Naples” (Figure 1). AMD...IFTLE 432: Ferric and TSMC Partner on Voltage Regulators; High TC Die Attach for TIM?
The IMAPS International Symposium took place this year in Boston. Let’s take a look at a few of the more...
IFTLE 431: Samsung Qualifies EDA Tools for Multi-die Integration
Samsung reports that they have seen increasing interest in multi-die integration (what they call MDI) for markets such as artificial...
IFTLE 430: Exascale Computing in Europe: Leading Edge Packaging is the Key!
Beyond HPC High-performance computing (HPC) has become an important tool for areas that generate high volumes of data. While today’s...