IFTLE 436: Fluxless µBumping; Latest on Stacking Technologies
Dec 27, 2019 · By Phil Garrou · Blogs, Packaging IFTLE
Latest Posts
IFTLE 438: Reliability Test For 0.3mm WLCSP; Copper RDL Trace Requirements
This week we continue our look presentations from SEMICON Europa’s Advanced Packaging Conference. Intel’s Reliability Test Beth Keser’s group at...
IFTLE 437: Packaging Trends for Artificial Intelligence
As it has in recent years, SEMICON Europa 2019 featured a dedicated Advanced Packaging Conference. In this and my next...
IFTLE 431: Samsung Qualifies EDA Tools for Multi-die Integration
Samsung reports that they have seen increasing interest in multi-die integration (what they call MDI) for markets such as artificial...
IFTLE 430: Exascale Computing in Europe: Leading Edge Packaging is the Key!
Beyond HPC High-performance computing (HPC) has become an important tool for areas that generate high volumes of data. While today’s...
IFTLE 429: Samsung 12-layer memory with 3D-TSV; SHIP Winners
Samsung Electronics has announced the development of 12-layer memory using 3D through silicon via (3D-TSV) chip packaging technology. TSVs vertically...
IFTLE 428: Panel Level Processing: We’ve Come A Long Way Baby!
It was in 1992 when Ted Tessier and I, in our paper, “Overview of MCM Technologies: MCM-D”, at the IMAPS...
IFTLE 427: TSMC’s Next-Gen 3D Technology – N3XT
Continuing our look out into the future, at the recent Hot Chips Conference, Dr. Phil Wong, VP of R&D at TSMC...
IFTLE 426: Exascale Computing is Near; Incandescent Lightbulbs get a Reprieve
Earlier this year, John Shalf, department head of Computer Science at Lawrence Berkeley National Labs (LBNL) presented a plenary presentation...
IFTLE 425: Deca FOWLP is Going Mainstream; Highlights from Hot Chips
Deca Technologies has confirmed that its M-Series™ fan-out wafer-level packaging (FOWLP) technology has been adopted by Qualcomm for power management...