High-performance computing (HPC) has become an important tool for areas that generate high volumes of data. While today's HPC is already powerful, many scientific and industrial challenges require even more computing power, for instance, drug discovery and material design. Thus, the global drive for exascale (1018) computing. »
Samsung Electronics has announced the development of 12-layer memory using 3D through silicon via (3D-TSV) chip packaging technology. TSVs vertically interconnect the two DRAM chips through more than 60,000 TSVs. Despite the increase in the number of layers from eight to 12, the overall thickness of the package remains at 720 µm so designers will not have to change dimensions to use the new techn... »
Remember when panel level processing was called large-area processing? Here, Phil Garrou provides a history lesson beginning from when he and Ted Tessier first presented the concept, to today's progress. »
Continuing our look out into the future, at the recent Hot Chips Conference, Dr. Phil Wong, VP of R&D at TSMC gave a presentation entitled “What Will the Next Node Offer Us?” where he discusses the use of chiplets, 3DICs, and a futuristic technology for the heterogeneous integration of memory and logic called N3XT, noting that this technology will be necessary after 3D in order to combine... »
Earlier this year, John Shalf, department head of Computer Science at Lawrence Berkeley National Labs (LBNL) presented a plenary presentation entitled “The Future of Computing Beyond Moore’s Law” (SEMICON West, July 2019). The premise espoused was one which you have read many times in IFTLE, i.e. now that CMOS scaling has come to an end: What’s next, and where are we going? Exascale comput... »
Deca Technologies has confirmed that its M-Series™ fan-out wafer-level packaging (FOWLP) technology has been adopted by Qualcomm for power management integrated circuit (PMIC) devices in Samsung’s S10, the Xiaomi Mi 9 and LG G8 smartphones. And in other news, advanced packaging was the Cinderella Story at Hot Chips 2019. »
IIFTLE is always on the lookout for technologies that will require advanced packaging solutions. Fingerprint sensors for today’s latest smartphones appear to be one of those applications. Packaging for Fingerprint Sensors DIGITIMes recently reported that the manufacture of under-display optical fingerprint sensors for use in 5G-enabled phones will require extensive wafer-level backend services... »
A year after GLOBALFOUNDRIES cancels its 7nm program, the company is developing 3D chip stacks fabricated using GLOBALFOUNDRIES’s 12nm FinFET process and features ARM’s mesh interconnect technology in 3D. This alternative to costly node shrinking may help GLOBALFOUNDRIES maintain a market presence. »
Is advanced packaging production coming back to the USA? The Navy (i.e. NSWC Crane) is currently seeking proposals from the industry for the development of technical and business plans to establish a secure on-shore design, assembly, and test capability. This facility should support the heterogeneous integration of state-of-the-art (SOTA) commercial integrated circuits (ICs) with defense specifi... »
Building on its previous announcements of embedded interconnect bridge (EMIB) and Foveros technologies, Intel recently provided details on three new enabling technologies for advanced packaging: Co-EMIB, managed data input/output (MDIO) and omnidirectional interconnect (ODI). »
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