As packaging practitioners/experts themselves, regular readers know that IFTLE is always on the lookout for the latest applications and the latest chips going into those applications because all those chips will have to be packaged. However, IFTLE has previously warned the reader to beware of technology hype, which appears to be increasing exponentially throughout the decades that I have lived. As... »
At the recent IMAPS Device Packaging Conference in Fountain Hills, AZ. Kyung Suk (Dan) Oh, Package Development VP at Samsung, discussed “Electronics Packaging Technologies for the 4th Industrial Revolution” Oh explained that Samsung sees today’s technology paradigm shift as going “beyond Moore” by a convergence of system integration/packaging and software. Based on the slide below, Oh sa... »
At the recent IMAPS Device Packaging Conference, March 5-7, 2019 in Fountain Hills AZ, Benedetto Vigna, president of the ST Micro Analog, MEMS and Sensors Group, discussed the company’s presence in the sensor technology market. The vast assortment of sensor and actuator functions have recently been defined by Yole Developpement as shown in Figure 1. 2018 IHS market data shows >50% of the ... »
Silicon Carbide (SiC) is a wide bandgap (WBG) material that has advantages when compared to silicon (Figure 1). For the same die size and thickness, WBG devices provide higher breakdown voltage, current, operating temperature, and switching speed; and lower switching loss over Si devices. ST Microelectronics (ST Micro) started working with SiC in 1996, producing its first SiC diodes in 2004. I... »
Continuing our look at the 2019 SEMI 3D and Systems summit in Dresden, we look at presentations on advanced packaging platforms and hybrid bonding reliability. Systems Plus Romain Fraux of System Plus discussed their analysis of the latest advanced packaging platforms on the market. The Yole Développement quantitative analysis of the market is shown in Figure 1: They offered the comparison slide ... »
Plasma Dicing Advanced packaging is bringing with it new ways to separate die from the wafer. In the past, wafer dicing was traditionally carried out using conventional dicing “saw”. However, this method has limitations such as die chipping or cracking leading to lower device yields. Also, the width of the blade removes valuable “real estate” from the wafer. Newer techniques include laser ... »
At CES 2019, Intel previewed a new client platform, code-named “Lakefield”. It featured the first iteration of its new innovative Foveros 3D packaging technology. The Lakefield stacked module will contain: 10nm hybrid CPU architecture Gen 11 graphics Multiple dies stacked on top of each other The die is then stacked using micro-bumps on the active interposer through which through silicon v... »
In this post, we interrupt our regularly scheduled conference review to look at some items that should be of interest to us all. Is GlobalFoundries (GF) Up for Sale? GlobalFoundries is currently the 3rd largest semiconductor foundry supplier with a reported 8.4% market share, just behind TSMC and Samsung. It has five 200 mm wafer fabrication plants in Singapore, one 300 mm plant each in Germany an... »
As scientists, we have a tendency to classify and categorize. It’s our way of comparing and contrasting things in our world. Some of these classifications stick and some don’t. For instance at the start of 3D a decade or so ago, Eric Beyne of IMEC laid out a perfectly reasonable classification of 3D structures based on the level of interconnect they were making. [ Link] It made all the sense i... »
In this IFTLE post, we continue our look at presentations from the 2018 EPTC Conference… Ultratech / IMEC / JSR – 1µm RDL Ultratech, IMEC and JSR discussed “One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging using a Photosensitive Dielectric Material”. This study compared the creation of 1.0μm RDL structures by a damascene process utilizing a photosensitive permanent d... »
Site Design By
Recent Comments