It’s almost ironic. As CMOS scaling (aka: Moore’s Law) has slowed due to the increased complexity and cost of achieving smaller nodes, the focus has shifted to advanced packaging and heterogeneous integration to meet demands for microelectronics devices targeting the internet of things (IoT) market. These devices perform a variety of functions (sensing, processing, remembering, transmitting) i... »
As Si interposer and 3D stacked memory devices enter into production, albeit in low volumes, semiconductor manufacturers are lining up their ducks to be ready for high volume manufacturing (HVM) when it happens. As a result, some suppliers of high volume manufacturing equipment who have been rather quiet through the development phase are now showing their cards. For example, KLA-Tencor recently in... »
A second side trip on the way to DATE 2015 brought me back to Nimes, France to check up on activities at Fogale Nanotech since last year. I was reminded once again, that Fogale isn’t just a semiconductor equipment supplier. Its core competencies are optical and capacitive sensing technologies, and thanks to the entrepreneurial spirit of the company’s CEO, Patrick Leteurtre, the compa... »
3D stacking is “already old hand”; or so declared Brion Keller, Cadence, in his keynote talk at last week’s 5th Annual 3D Test Workshop, which took place in Seattle, October 23-24, 2014. In his presentation, 3D Rock from the Sun, Keller talked about the wonders of technological progress, and how we are pulled in the direction of 3D integration because there are products that will have no ot... »
My visit to imec to meet with the Cascade Micorotech and imec 3D Test collaboration team included a tour of the 3D test lab to see the CM300 in action, so we suited up for Class 1000 cleanroom and stepped inside. Generally we would have had to prep for class 100 or higher for the test environment, but thanks to nifty new FOUPs that have a class 1 microenvironment to protect the wafers, we at least... »
For quite some time, the lack of cost-effective test solutions for 2.5D interposers and 3D stacked ICs (3D SICs) has been at the top of many industry experts’ laundry list of ‘what’s-holding-up-commercialization for 3D’. First, there are technology issues: fine-pitch probing, pin count, contact force and the phenomenon of weak I/O drivers. But bigger than that, the cost of 3D test is a maj... »
The Friday 3D Integration Workshop at DATE 2014 once again found me among friends, as an intimate group of about 30 gathered to spend a day sharing knowledge gained since last year’s workshop. My key take-away for the day was how to achieve reliability and robustness. Jürgen Wolf, director of the Fraunhofer IZM-ASSID 3D integration program stepped in as keynote speaker to replace Yole Développ... »
In the world of 3D ICs, where features are becoming finer and submicron accuracy and precision is more important than ever to maintain intra-wafer uniformity throughout the wafer or die stacking process flow, process control by means of metrology and inspection is more important than ever. The industry offers a number of non-destructive options – optical, X-ray, scanning acoustic microscopy – ... »
Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for 2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool and design flow changes need to be evolutionary, rather than revolutionary.” A... »
In Jan Vardaman’s recent readiness report card issued at 3D ASIP in December, 3D IC thermal management issues scored and “F” for lack of a solution o the hot-spot problem when stacking memory on logic. And while she gave 3D IC test a “B” for probe card development, it got an incomplete for reliability data. At the end of her presentation, she invited anyone with new solutions to “see ... »
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