The Evolution of Inspection and Metrology in the AI Era
Apr 28, 2025 · By Camtek · 3D In-Depth, Test and Inspection
Latest Posts
Chiplet Test: Piecing Together the Next Generation of Chips (Part 2)
Testing the limits: standardization and optimization of chiplet test protocols Chiplets often come from different sources, making electrical testing challenging....
The Year in Semiconductor Device Test
Is semiconductor device test non-value added? Certainly, some aspects are unchanging. Test is one of the three means to guarantee...
How is X-ray Inspection Used in Semiconductor Manufacturing?
Technology is Key With the ever-present pressure to produce more efficient devices with more power, the sizes of the structures...
Thermal Test Chips (TTCs) for Advanced Semiconductor Packaging
Thermal management is becoming an ever more critical challenge for semiconductor devices, as the functional density and power density increase...
A Look at the Next Generation of Packaging Inspection Solutions
With the increasing expectations and demands of customers of electronic equipment, the manufacturing technologies applied are also propelled due to...
Excitement Over Chiplets: Not for Everyone and Not Trivial for Test
Live from “Silicon Desert”: The news is all about huge spending by TSMC and Intel. Investment in advanced packaging (2.3/2.5/3D...
Digital and Physical: Thermal Twins for Developing Thermal Management Solutions
As we all know, finding thermal management solutions is becoming an increasingly critical but also an ever more challenging issue...
Updates in Test Connectivity System (TCS) from TestConX
The annual TestConX conference (www.testconx.org) was held March 5-8, 2023, in Mesa, Arizona. It offered a one-of-a-kind, one-stop shop for...
SiC MOSFET Challenges, Demand and Industrialization of Test & Burn-in
The coming-of-age and breakthroughs offered by silicon carbide (SiC) MOSFETs, as well as demand that is outstripping supply are rapidly...
Update on the UCIe™ from ITC 2022
In 1965 Gordon Moore proclaimed that there would be a “’Day of Reckoning’ when it may prove to be more...
Advanced Packaging – Measuring Deep Etch Trenches
Adoption of advanced packaging is accelerating as the benefit of the classic Moore’s Law transistor shrink diminishes on a monolithic...
Metrology in Advanced Packaging
With the dawn of chiplet integration, advanced chip manufacturing and advanced packaging technologies are more complex than ever. Dies are...
Maximize Large Volume Failure Analysis Throughput with Parallel Processing of Laser Ablation and Plasma FIB
Determining the causes of failures in semiconductors often requires removing overlying material to expose the failed circuit element for high-resolution...
Artifact-free Decapsulation of 2.5D and 3D Advanced Packages
As semiconductor devices are subject to increasingly higher quality and reliability standards, extensive measures must be taken to ensure these...
The Importance of Product Burn-In Test
Introduction Product burn-in (BI) is an indispensable step in the production test flow to ensure good quality and a properly...
IFTLE 476: 2020 3D Test Workshop – IMEC Co-Packaged Optics & Intel Foveros Testing
November 2020 saw the 7th IEEE International Workshop on Testing 3D, Chiplet-Based, and Stacked ICs (which IFTLE has been calling...
Meeting the Challenges of 5G RF Production Test Services
Implementation of the 5G radio frequency (RF) standard is increasing rapidly [1]. Over the past four to six quarters, there...
Process Control and Inspection for High-Value Advanced Packages: It’s Complicated
In September of 2018, I spoke with KLA’s Stephen Hiebert and Pieter Vandewalle about the changing advanced packaging landscape, and...
Why We Need to Address Known Good Die (KDG) Holistically
If you love, like me, to work on the bleeding edge of technology, you will find that your personal success...
