Metrology, process control, and electrical test are key enablers for the success of the semiconductor industry. 3D integration using TSVs offers new challenges in this area that need solutions. There seems to be industry consensus that it is extremely difficult to perform a wafer-level test that ensures the complete functionality of the TSVs. There are ideas about how to perform 3D TSV test with ... »
Here’s one thing the team at Rudolph has a firm grasp on: understanding that feature sizes of today’s wafer-level, 2.5D and 3D packaging technologies are changing the requirements for manufacturing tools in the back-end, and in many cases the back-end tools of today are starting to resemble the front-end tools of yesterday. Unfortunately, these tools are still expected to come at back-end tool... »
As this year’s 3D IC Test Workshop unfolded (September 12 & 13, 2012), one thing became increasingly clear to me: the challenge of probing microbumps is an item of critical concern in 3D test. During the panel discussion on test requirements for 3D ICs, Saman Adham of TSMC Canada, noted that currently, microbump probing is extremely difficult and we need a better way to probe. Qualcomm’s A... »
This past July, I visited Multitest’s San Jose location to learn about the company’s activities in 3D IC test, as well as gain a better understanding of the company’s Plug & Yield™ philosophy, which spans handler, contactor and load board technologies. Earlier this month, the company announced its acquisition by LTX-Credence, along with its sister company, Everett Charles Technolog... »
What better way to wrap up a busy week at SEMICON West 2013 than a site visit? After three days of interviews and PowerPoints, I was ready for some some hands-on demonstration. Barbara Loferer, marketing manager of Multitest, was concluding an open-house week at the company’s San Jose facility to promote the company’s current focus on the mobility market and subsequent product enhancements, a... »
This is part of a series of short interviews, based on face-to-face meetings at SEMICON West 2013. For a long time, the jury was out on the probe-ability of micro-bumped TSV wafers. The jury was also unsure whether or not there was any point to probing to ensure known good die (KGD) or will “probably good die” suffice, given the cost of test? Probe test companies, FormFactor and Microprobe wer... »
This is part of a series of short interviews, based on face-to-face meetings at SEMICON West 2013. As 3D ICs get closer to volume manufacturing, we’re seeing newcomers joining the 3D IC party with solutions that help along established process flows, and fill in gaps. Longtime suppliers to the mainstream advanced packaging market, NORDSON Dage and NORDSON March, have each identified areas in 3D I... »
New this year at SEMICON West, and just introduced to the program late last week, the Expert TechHUBs will help attendees find answers to specific semiconductor test and packaging questions. Meet with industry experts in an informal discussion group on the North Hall show floor at TechHUB Test or in TechHUB Assembly & Packaging. The Hubs will be held on Tuesday and Wednesday from 11:00am – 4... »
Subscribers are practically blowing up 3D InCites as they duke it out online and race the July 3rd deadline for casting their ballots in the public opinion poll for this inaugural 3D InCites Awards; which is great because the first 3D InCites Awards Breakfast, co-presented by 3D InCites and TechSearch International, is fast approaching, and we’ve got an exciting program shaping up. We’re hap... »
The 2013 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher band... »
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