Reliable Process Control Solutions for the Growing Power Device Market

Reliable Process Control Solutions for the Growing Power Device Market

The expected increase of the power device market, with a compound annual growth rate (CAGR) of more than 10% — and more particularly insulated-gate bipolar transistor (IGBT) products for automotive and other applications — is pushing the semiconductor industry to adopt specific process solutions. The maturity of IGBT market, boosted by booming demand for electrified vehicles (EV) and hybrid electrified vehicles (HEV), and the consequent need for improved manufacturing yield to stay economically competitive, has forced several device makers to collaborate with their supply chain in developing ad-hoc process control solutions.

Figure 1: Fabrication process flow of IGBT power device

Figure 1: Fabrication process flow of IGBT device

For several years, Unity-SC has collaborated with major IGBT makers to secure the most critical fabrication steps in the manufacturing chain from the front-end down to the advanced packaging area. More specifically, the company has focused its efforts to develop non-conventional solutions for the wafer thinning area.

In fact, thanks to the reduction in wafer thickness, shorter wiring or through silicon via (TSV) pitch can be reached and simultaneously package size miniaturization targets are met, while simultaneously enhancing the device performance and reducing power loss.

In the typical process flow used for IGBT fabrication, the backside thinning is identified as one of the most critical steps (Figure 1).

Back grinding is the most popular process method used to reduce the wafer thickness because it is a low-cost and high-speed technique. However, the mechanical stress and heat applied during this process generate damage that can be removed by using different methods to improve the final surface finish. Nevertheless, any remaining defect on the backside surface may generate final defective dies.

In-line control of the device thickness and its integrity from defectivity perspective are a must to secure the product functionality and prevent future failures once in use on EV/HEV.

Thickness control

Fabrication specifications for the thickness of the final package are often connected to reliable performance. Consequently, measurement methods with good Gage repeatability and reproducibility (GR&R) at key device locations must be chosen.

In the example illustrated in Figure 2, the wafer is glued on a temporary carrier to support it during the thinning process. The thickness of four material layers is simultaneously measured by combining two interferometric point sensors that use time-domain analysis to control all layers from both sides of the structure. The integrated visual capability of the measurement sensors allows the identification of the embedded target non-visible at the surface by looking for its pattern at sub-micrometer precision through the silicon with near infra-red (NIR) microscopy.

power device market

Figure 2: Simultaneous thickness measurement of a four-layer stack at gate area. From top to bottom: Silicon/metal/adhesive material/glass carrier.

The measurement capability is reached on a stack that includes transparent material like Si or adhesive, and opaque material like metals, where thicknesses for each layer may vary from a few microns up to almost a millimeter. On a metrology tool only capable of addressing one-layer thickness at the time with a dedicated technique, this would require stopping the wafer. Today, however, the device maker can choose metrology platforms like the TMAP Series from Unity-SC, which combines complementary technologies and an optimized optical design to address all the metrology control in one single step. This translates to a considerable reduction in operational cost for the device maker.

Using complementary information gathered while measuring the thickness, the TMAP series can quantify the bow/warp and the total thickness variation (TTV) of the bonded wafer and prevent the wafer from continuing through the production line if it is no longer within the specifications. This avoids wafer breakage in the fab that incurs costly equipment downtime.

Backside thinning quality control

The aggressive backside thinning process needed to reduce package size has the potential to introduce latent defects that might cause device failure even years later after its fabrication. Traditional automatic optical inspection systems are not sensitive enough to catch killer defects with very low optical contrast.

Unity-SC has developed proprietary detection technologies capable of detecting all critical anomalies. For example, phase shift deflection (PSD) is a powerful technique that guarantees detection of topographic defects in a height range of only a few nanometers and at an inspection rate of 100wph.

PSD is used to inspect the backside surface and generate complementary whole wafers images, each one used to extract different digital optic identifiers (DOIs) and wafer macro properties (Figure 3). Topographic defects like comets, surface dislocations, and star and hair cracks can be detected and separated from grinding marks through automatic defect classification (ADC) analysis of the curvature image, while stains and residues are extracted from the reflectivity image. Additional information on the wafer’s global integrity is reachable from the topographic map.

processes for the power device market

Figure 3: Quality control strategy and DOI detectable by 4SEE series from Unity-SC equipped with deflector module.

As a complementary option available on the 4SEE series from Unity-SC, the edge of the wafer can be inspected by 2D line scan technology based on confocal chromatic imaging. The natural extended depth of focus provided by the chromatic lens is the perfect tool to recognize chips, cracks, and contamination located at the five zones of the bevel area (top, top bevel, apex, bottom bevel, bottom), that can propagate on the wafer during process stress conditions and damage the dies.

Handling challenges

Besides the measurement difficulty, another major challenge is wafer handling during the thinning process. In fact, when the wafer’s thickness is reduced from several hundred microns down to few tens of microns, the mechanical property of the silicon substrate prevents the wafer from being moved across multiple processing tools without ad hoc solutions. Any device maker is forced to finding the best approach to overcome the handling limitations at a sustainable cost. The wafer can be temporarily bonded on a silicon or glass carrier, it can be transformed to a Taiko wafer, or mounted on a dicing frame. Notch-detection on dirty bonded wafers and the need for partial or full contactless handling are examples of the additional capabilities faced by equipment manufacturers.

As supplier a of leading-edge inspection and metrology equipment worldwide, Unity-SC is committed to developing reliable solutions to meet any specific fab requirement. Investments in internal development, as well as mergers and acquisitions over the last two years, provides customers with the validity of our process control capabilities, and the uniqueness of our contribution to secure their fabrication processes.

Today, with several 4SEE and TMAP systems in use at IGBT makers, thanks to the bilateral collaboration with our partners, our product portfolio is ready to serve almost any customer need in semiconductor thinning wafer industry.

Editor’s Note: This article also appears in 3D InCites: The First Decade. Download the full issue here.