Test and Inspection

3D Technology Features in Review

The latest digital issues of Chip Scale Review and  iMicronews’ 3D Packaging magazines hit the virtual “stands” last week, and perhaps in honor if the 3D ASIP Conference that gets underway later this week, there are some hot new 3D technologies being featured. But first, to bring everyone up to speed, Jan Vardaman and Linda Mathew, TechSearch International, co-authored an editorial titled ... »

3D IC Educational Opportunities

If you have an hour of professional development time coming to you, I advise that you spend it watching this webinar on TSV and Interposer: modeling, design and characterization, presented by Darryl Kostka, of Computer Simulation Technology (CST).  But don’t just take my word for it! It comes highly recommended by Bill Martin of E-System Design, who posted this comment on LinkedIn: “a perfect... »

The Stacked Die Reality Check Continues; FPGAs Lead the 3D Charge

It’s been one of those Mondays. I started making the coffee this morning (put in a clean filter, poured in the water) before I got sidetracked and hit the shower without ever putting in the grounds or turning it on. Then I left the Impress Labs office without my key at lunch to run an errand and came back to a locked office front door. So I tried the main entrance and got as far as the communal ... »

Apple iPhone 5 Teardown; More on FinFets; Thoughts on 3D Test; (and some Friday Fun at the End)

Somehow the social media “shares” on Friday are more lighthearted than the rest of the week. Today, all the excitement was divided up between the iPhone 5 teardown and the last flight of the spaceshuttle Endeavor, as it toured its way up the California coastline riding piggyback on a 747. Here’s a link to collected tweets at #spottheshuttle  and #endeavor, and a great video shot by the MCA »

Design and Test Solutions are Trending in 3D ICs

These days, as I troll the pages of the Internet in search of juicy tidbits of 3D IC news and information, I’ve realized that with the exception of that pesky issue with thin wafer handling, focus has moved away from novel manufacturing processes, and turned its magnifying glass onto the world of design, test, reliability, signal and power integrity, ESD challenges, and so forth. This is proving »

Perspectives on 3D Integration: The Researchers

To listen to John Lau, of ITRI, speak on the topic of 3D integration is to experience a passion for technology that rivals no other; except perhaps that of Rao Tummala of Georgia Tech.  But John is definitely more vocal in his passion. Rao has a softer, gentler approach.  At this year’s IWLPC in Santa Clara, both expressed their perspectives on what they see as the most cost effective ... »

3-D chips and Evolving Test Strategies Take Center Stage at ITC

Program chair Erik Volkerink of Verigy discusses this year's International Test Conference in an interview with Rick Nelson, Chief Editor, Test and Measurment World. The testing of 3-D chips, protocol-aware test, and concurrent test will be key topics on the agenda of the 41st International Test Conference October 31 through November 5 in Austin TX. While the test of 3-D chips was a key focus at ... »

DATE’10 3D Integration Workshop addresses applications, technology, architecture, design, automation, and test’

3D Workshop organizers Erik Jan Marinissen (IMEC), Yann Guillou (ST-Ericsson) Geert Van der Plas (IMEC) report back from a very successful second year at DATE, 2010 in Dresden, Germany. »

Bringing Transparency to 3D Integrated Structures – Olympus Confocal IR Microscopy

Metrology is consistently one of the more challenging areas in the semiconductor field. Whether it’s the monitoring of ultra-small features and defects, or inspecting the backside or bevel of a wafer, the challenges are ever growing. The situation is further complicated by the need for in-line metrology that can be used in the fab during device manufacturing as distinct from out-of-line failur... »

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