3D Workshop organizers Erik Jan Marinissen (IMEC), Yann Guillou (ST-Ericsson) Geert Van der Plas (IMEC) report back from a very successful second year at DATE, 2010 in Dresden, Germany.

The 2010 edition of the Design, Automation, and Test in Europe (DATE) conference, which took place in Dresden, Germany, hosted the second edition of the workshop on ‘3D Integration’ on Friday March 12, 2010. Vertical stacking of multiple silicon dies, interconnected by through-silicon vias (TSVs) is a promising technology. It offers higher transistor density, faster interconnects, heterogeneous technology integration, and potentially lower cost and time-to-market.

Unique about this workshop is that it approaches the topic of 3D integration not only as a processing, packaging, or design issue, but instead discusses it from all angles: applications, technology, architecture, design, automation, and test. The topic is ‘hot’, and with over 75 registered attendees, the workshop was the most popular of DATE’s Friday workshops for the second year in a row.

The workshop opened with a keynote address by Cheng-Wen Wu, ICL director at ITRI and professor at National Tsing-Hua University, both in Taiwan. Titled What We Have Learned From SOC is What is Driving 3D Integration, he argued that older CMOS technologies continue to live also, and especially thanks to 3D integration. Wu also addressed the challenges of testing and redundancy of TSV-based ICs.

The second keynote address was by ChoonHeung Lee of Amkor Technology, Korea. Tn his presentation, ‘OSAT – Role as Partner in 3D Integration’, he outlined that TSV-based stacking fits in a natural evolution of the packaging roadmap that has been experiencing 3D integration already for years.
Subsequent paper presentations discussed applications (a 3D CMOS imager), architecture (Network-on-Chip architecture), design (thermal TSVs), technology (high aspect-ratio TSVs and temporary wafer bonding), and test (TSV open defects). The program also contained 25 posters, which were on display during two dedicated and lively poster sessions, offering workshop participants the opportunity for direct interactions.

The day was closed by a panel session under titled “3D: A Reality?”, which  was skillfully moderated by Jean-Christophe Eloy of Yole Developpement. The first two panelists represented the semiconductor industry: Jochen Reisinger of Infineon Technologies, Germany, and Damien Riquet of ST Microelectronics, France. Next up was embedded IP provider Rob Aitken of ARM, USA. Finally, the stage was turned over to EDA representatives Vassilios Gerousis of Cadence Design Systems, USA and Rajiv Maheshwary of Synopsys, USA.

The workshop produced an Electronic Workshop Digest, including abstracts, papers, slides, and posters (totaling 425 pages!). This digest is available here for download at the workshop’s web site. Actually, also the digest of last year’s workshop is still available for download.

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