The latest digital issues of Chip Scale Review and iMicronews’ 3D Packaging magazines hit the virtual “stands” last week, and perhaps in honor if the 3D ASIP Conferencethat gets underway later this week, there are some hot new 3D technologies being featured.
But first, to bring everyone up to speed, Jan Vardaman and Linda Mathew, TechSearch International, co-authored an editorial titled Why Does it Take So Long to Introduce New Technologies? – A Lesson for 3D IC Adoption that appears in Chip Scale Review, in which they explain, through historical comparison with other process introductions such as flip chip interconnect, why the process seems endless. In contrast, Vardaman and Matthew provide an early adopter case study of Xilinx development and introduction of a 3D IC product via its 28nm Virtex-7 LX200T field-programmable gate array (FPGA). Xilinx, which took only five years to bring to market from initial R&D work in 2006 to product launch in 2010, thanks to a commitment of time, resources and particularly commitment to design software.
The issue also includes two technology features that provide solutions to some remaining challenges; namely thin wafer handling, and metrology and inspection. In 3D IC Thin-Wafer Handling Materials Requirements, Brewer Science’s Mark Privett talks about one of the rarely discussed issues – material requirements for full backside processing involved in wafer thinning, the capabilities, and processing of the currently available material sets.
Rajiv Roy, Tim Kryman, and Reza Asgari of Rudolph Technologies, authored and article titled Metrology and Inspection Solutions for TSV Processes Used to Connect 3D Stacked ICs, which explains how each TSV process step – etch, fill, and interconnect – has unique inspection and metrology requirements necessary for process control. This article examines them all and offers viable solutions.
iMicronews’ latest issue was produced in collaboration with Amkor, and as such features a couple stories contributed by the OSAT. One introduces its latest non-TSV low cost alternative, which leverages the company’s s expertise with Chip-on-Chip (CoC) and face-to-face device integration. The die design has been dubbed “Possum” because “it describes two or more devices assembled face-to-face where a smaller die is nested within I/O-free areas of the larger die. The larger of the two dies is referred to as the mother die and the smaller one is called the daughter die.” Double Possum is said to offer dense 3D packaging without TSVs.
In OSAT positioning in the emerging Mid-End: Fan Out, 3D ICS and 2.5D Multi Die Interposers, readers get a first-hand look at how Amkor is positioning itself in these markets. Aside from being a great commercial for Amkor, the article does provide a good overview of the technologies’ progress, challenges and benefits.