After 20 years of chasing elusive Known Good Die (KGD) to achieve high yielding advanced interconnect technologies, the semiconductor industry has come to the conclusion that its time to take a different approach. It’s called Probably Good Die, and when it comes to 2.5D and 3D ICs, particularly for Memory, it’s a means to an end. At Known Good Die 2012: Reducing Costs through Yield Optimization, this message rang loud and clear throughout many of the presentations, and during the panel discussion.

The bulk of requirement for KGD is in Memory, says Abe Yee, of NVidia, manufacturer of graphics processors. The company’s next-generation high performance GPU is a 28nm device with an enormous amount of vias connecting the chip at the smallest feature sizes possible. “The process window for contact vias is very small,” says Yee. “It’s challenging and not getting easier. The bad news is EUV won’t be ready for 10nm.” Calling the graphics processor “GPU on steroids”, he noted that it doesn’t work by itself, but memory bandwidth has not kept up. “We need Wide I/O memory to feed the engine,” said Yee. “We need known good stacked die. 2.5D is not enough for NVidia’s needs. “

But die yield loss limits manufacturability for 3D ICs, and it’s expensive to do wafer-level burn-in test says Terry Caskey, of Invensas. He explained that it’s not just a yield problem, it’s associated with liability issues, which makes it a business problem. Multi-chip module (MCM) yield loss lands on the assembly houses. Alternatively, monolithic system-on-chip (SOC) yield loss is assigned into the fab, which is easier for the supply chain to handle. “One of the most successful solutions is to avoid it altogether.” Says Caskey. “and design around it with Monolithic SoCs and package on package (PoPs).”

While all eyes are on the TSV solution for processor-memory stacks, KGD problems need to be solved. At Invensas, they’re doing something different. They’ve developed the Bond Via Array PoP (BVA PoP); a standard 14mm PoP assembly using the existing infrastructure but allows for higher I/O.

Built in redundancy helps with KGD in memory devices noted Richard Otte or Promex Industries. He suggests instead of demanding KGD, we build the assembly for rework. This will require a different design philosophy than the one in place today. Rather than starting at the die level and throwing the ball to the next, we should approach it from the system level and design systems that tolerate defects and failures.

Otte also noted that the whole KGD issue is a function of application. We always talk about leading-edge applications.  But what about the automotive industry, which is large but everything is not leading edge. “There are lots of applications where you can make KGD by picking technology that is very robust, and move away from advanced nodes.”

But 3D is something you can’t get another way, says Bob Patti. It precludes safe nodes of technology. While we’re at it, design for test isn’t good enough anymore either.  What we need, says Patti, is a new concept: Design for Repair. He should know, his company is the only one who is already producing 3D stacked memory using fine-grain TSVs filled with Tungsten rather than Copper because “Tungsten just performs better,” says Patti.

“Memories are the poster child for design for repair, We disintegrate the memory and get twice the number of memory cells,” says Patti. The results: All the performance of high-speed logic with all the retention characteristics of the DRAM process. it’s repairable and gets good yield.

“We are better yielding in 3D than we are in 2D,” says Patti. “3D allows us to do something that 2D doesn’t; if we have a failure we can borrow repair structures from other layers. The bigger I make the memory, the more repairable it is.” We have to change the way we think about design, and 2.5D and 3D have to drive new solutions.

Test capabilities are getting there to ensure lower cost, says Herb Reiter, eda2 asic. This is a clear win for 3D, and he says he’s happy to see the progress of test in the past few years.  What’s missing, he says, is engagement from the EDA community to make cost effective designs for 3D. System designers assess what 3D can do for you. Pathfinding is extremely important. There should be a capability to design in redundancy.  “Why are we refusing to design in redundancy when its clear how efficient and effective it is to have redundancy designed in?”  He asks.

Not everyone is giving up on KGD quite yet.  Gary Fleeman, of Advantest says that the industry is getting closer to KGD and known good stacks (KGS).  “I don’t like ‘probably good die,” he says. “I believe in KGD and we’re going to try and get there. Each interim product must be a Known Good Product.” Fleeman believes that KGD are essential to making 2.5 and 3D stacking cost effective.  At Advantest, they are working on a non-conventional test methodology that enables KGD. He talked about work being done by IEEE and Erik Jan Marinissen’s team at imec. There are many new test points that will be selectively implemented. Each flow will use different points. No flow will use all the points. The key is tooling, flexibility and integration.

Cascade Microtech is also in the KGD cheering section, and Ken Smith of Cascade presented an update on the company’s 3D TSV probe card architecture. The cornerstone of this work for probing TSVs is what the company calls rocking beam interpoer (RBI). While this technology is still in early stages of development, Smith says this work proves probing microbumps is feasible.

But the bottom line is this: We need 3D ICs, so we’re going to have to do it without relying on KGD. Building in redundancy, self-test, and repair will make PGD good enough. I predict that next year, this conference will have changed its name to the Probably Good Die Symposium.  Has a nice ring to it, don’t you think?  ~FvT

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