Every year in early March, I spend a day at the BiTS Workshop (Burn-in Test Strategies), not because it’s a hotbed of 3D technology information (although this year there were some papers addressing 3D test as solutions are now becoming available) but because I’ve been working with the General Chair, Fred Taber, for years, first during my tenure at Advanced Packaging Magazine, and then at Chip Scale Review. On one occasion, Fred recruited me to deliver 3D technology updates, and I’ve helped out the workshop by lending my interview abilities for keynote and exhibitor videos.
This year, I was asked to host Talking Points, a talk show format panel discussion. The topic was Interconnectology; inspiring a Paradigm Shift. I was the “host” and our “featured guests” included Scott Jewler, of ANS, Inc; Sitaram Arkalgud, of Invensas; Chris Scanlan, of Deca Technologies; and Ira Feldman, of Feldman Engineering. What ensued was a very lively discussion about the importance of a system-level approach to semiconductor device manufacturing as technologies continue to become more complex and require a diverse skill set spanning the entire value chain. Interconnectology is the science that will bring this about.
The overall message of Talking Points dovetailed nicely with points Bill McClean of IC Insights had made earlier in the day in his keynote address, “The Dramatic Restructuring of the Integrated Ciruit Industry” when he touted the cost advantages that 3D ICs can bring to the overall system costs.
McClean explained that the original bottom-up business model that depended on capacity and capital spending has given way to a top-down model that is more consumer-driven, and dependent on what happens with the world-wide Gross Domestic Product (GDP). While there will still be cycles and fluctuations, McClean says this they won’t be as dramatic and will be linked to the normal cycles of the worldwide economy.
Additionally, McClean explained the toll increased transistor costs will take on overall price/performance ratio. Essentially, if the price per transistor doesn’t come down or even goes up, its impossible to achieve the improved performance benefits we have come to expect, and as such may extend time where consumers upgrade cell phones from 2 to 3 years. 3D interconnect technologies as well as other wafer-level integration options is one way to address this by keeping the total system cost down. McClean talked to me about this during a video interview at BITS Workshop. Here’s a clip of that video, the entirety of which will be published soon on the BiTS Workshop Website.
During the discussion period of Talking Points, one of the attendees commented that the concept of interconnectology – with collaboration across the value chain from concept to commercialization – is something the burn-in test industry has been waiting to hear for a long time. Many of these lessons were learned as a result of the development of 3D IC technologies, and hopefully they will be carried through with the next wave of emerging technologies so that time to market will be quicker, and what can and can’t be done at the burn-in test level will be understood from the get-go.