Somehow the social media “shares” on Friday are more lighthearted than the rest of the week. Today, all the excitement was divided up between the iPhone 5 teardown and the last flight of the spaceshuttle Endeavor, as it toured its way up the California coastline riding piggyback on a 747. Here’s a link to collected tweets at #spottheshuttle and #endeavor, and a great video shot by the MCA team below:
For those people in its path, this will surely be one of those days where you can say “I remember where I was when….”
I have to admit, since I’m sitting in Phoenix without a chance of catching even a glimpse of the shuttle, I was more excited to find out what’s inside the iPhone 5. At this writing, Chipworks has provided an initial teardown list, and some details on the camera and battery, identifying the primary image sensor (Sony); and secondary image sensor (Omnivision). So far the A6 processor has yet to be confirmed beyond the markings, although there are strong suggestions it might be procured from Samsung. You can read more about it on the Chipworks blog here.
Today brought a couple more FinFET-focused posts offering some fresh insight on yesterday’s announcement by GlobalFoundries regarding its 14nm XM technology. SemiMD’s Brian Bailey and Mark LePedus teamed up to write More FinFETS Arrive. Here’s something new I learned from this about FinFETS: according to the post, the “fins” of FinFETs increase electron’s travel area, which improves control over the “on” and “off” states, thereby reducing leakage. Since leakage generates heat that can cause havoc to the signal integrity and performance of stacked die (among other high density devices) this is important. And specific to GlobalFoundries strategy, the modular approach to this 14nm FinFET built on a 20nm MEOL/BEOL flow reduces the risk and increases time to market, potentially putting them ahead of their process roadmap by a year.
In his post on EDN titled, Growing up in the Third Dimension, Brian Bailey (yes, the same guy who co-wrote the SemiMD post – the guy gets around!) does a great job expanding further on the benefits of FinFETS as we go below 22nm, as well as differentiating them from 3D ICS, and noting at the end how the two technology advancements combined “mean that there is no end in sight to system complexity.” (Which is another reason why 3D InCites should follow both!)
After hearing various speakers at IMAPS last week try to will away the need to test 3D ICs at each level in order to save manufacturing costs, I found Ed Sperling’s opinion expressed in his blog post on SemiMD, Testing, Testing, One, Two, Three, to be much more realistic. In it, he talks about the “black boxes” and how “they can turn bad on their own, and they can start out good and perform miserably when combined with other black boxes.” Sperling goes on to write: “test needs to be part of the initial design architecture, and it needs to follow right through to the manufacturing because there’s no such thing as a single test. Testing needs to be internal, external, and in stacked die it needs to be done before and after packaging.” This is something I hear a lot from the test guys. I think the manufacturing guys need to listen before just tossing the need for interim test out the window.
I promised some Friday fun if you read (or at least scrolled directly) to the end of this post. Here it is, shared with me by Ken Mason, aka @nanolithoman on Twitter. Who says geeks don’t know how to have fun? ~ F.v.T.
