IFTLE 462: If Not a Node then What?
Sep 22, 2020 · By Phil Garrou · Blogs, Packaging IFTLE
Latest Posts - Page 2
IFTLE 438: Reliability Test For 0.3mm WLCSP; Copper RDL Trace Requirements
This week we continue our look presentations from SEMICON Europa’s Advanced Packaging Conference. Intel’s Reliability Test Beth Keser’s group at...
IFTLE 437: Packaging Trends for Artificial Intelligence
As it has in recent years, SEMICON Europa 2019 featured a dedicated Advanced Packaging Conference. In this and my next...
IFTLE 436: Fluxless µBumping; Latest on Stacking Technologies
The November Issue of Chip Scale Review contains some interesting advanced packaging information that is worthy of sharing in IFTLE:...
IFTLE 435: The Heterogeneous Integration Roadmap (HIR)
Before we start this week’s blog, let me take the opportunity to wish all IFTLE readers a Merry Christmas and...
IFTLE 434: Process Optimization for a Reliable NXP FOWLP Microcontroller
There are several different fan-out wafer-level packaging (FOWLP) technologies that are currently in high-volume production. The traditional fan-out (FO) technology...
IFTLE 433: AMD Chiplets go Commercial Amidst a Need for Chiplet Standardization
In 2017, AMD used chiplets in their “Zen 2” architecture to develop the Epyc server processor “Naples” (Figure 1). AMD...IFTLE 432: Ferric and TSMC Partner on Voltage Regulators; High TC Die Attach for TIM?
The IMAPS International Symposium took place this year in Boston. Let’s take a look at a few of the more...
IFTLE 431: Samsung Qualifies EDA Tools for Multi-die Integration
Samsung reports that they have seen increasing interest in multi-die integration (what they call MDI) for markets such as artificial...
IFTLE 430: Exascale Computing in Europe: Leading Edge Packaging is the Key!
Beyond HPC High-performance computing (HPC) has become an important tool for areas that generate high volumes of data. While today’s...
IFTLE 429: Samsung 12-layer memory with 3D-TSV; SHIP Winners
Samsung Electronics has announced the development of 12-layer memory using 3D through silicon via (3D-TSV) chip packaging technology. TSVs vertically...
IFTLE 428: Panel Level Processing: We’ve Come A Long Way Baby!
It was in 1992 when Ted Tessier and I, in our paper, “Overview of MCM Technologies: MCM-D”, at the IMAPS...
IFTLE 427: TSMC’s Next-Gen 3D Technology – N3XT
Continuing our look out into the future, at the recent Hot Chips Conference, Dr. Phil Wong, VP of R&D at TSMC...
IFTLE 426: Exascale Computing is Near; Incandescent Lightbulbs get a Reprieve
Earlier this year, John Shalf, department head of Computer Science at Lawrence Berkeley National Labs (LBNL) presented a plenary presentation...
IFTLE 425: Deca FOWLP is Going Mainstream; Highlights from Hot Chips
Deca Technologies has confirmed that its M-Series™ fan-out wafer-level packaging (FOWLP) technology has been adopted by Qualcomm for power management...
IFTLE 424: Fingerprint Sensors Are Going Ultrasonic
IIFTLE is always on the lookout for technologies that will require advanced packaging solutions. Fingerprint sensors for today’s latest smartphones...
IFTLE 423: GLOBALFOUNDRIES and ARM Turn to 3D Chip Stacks for High Performance Computing
It was exactly a year ago that GLOBALFOUNDRIES’ announced that they would no longer be competing in the node scaling...
IFTLE 422: Is Advanced Packaging Production Returning to the US by SHIP?
Is advanced packaging production coming back to the USA? The Navy (i.e. NSWC Crane) is currently seeking proposals from the...
IFTLE 421: Intel Showcases Co-EMIB Advanced Packaging Architecture
Building on their previous announcements of its embedded interconnect bridge, EMIB, ( see IFTLE 324 “Intel EMIB Implementation in the...IFTLE 420: Low-Loss NCF and Laser-Assisted TCB
Since it first appeared several years ago, IFTLE has been a big-time proponent of pre-applied non-conductive film (NCF) combined with...