Packaging IFTLE

IFTLE 409: ST Micro Studies Hybrid Bonding Reliability; TSMC 2019 Packaging Revenue

IFTLE 409: ST Micro Studies Hybrid Bonding Reliability; TSMC 2019 Packaging Revenue

Continuing our look at the 2019 SEMI 3D and Systems summit in Dresden, we look at presentations on advanced packaging platforms and hybrid bonding reliability. Systems Plus Romain Fraux of System Plus discussed their analysis of the latest advanced packaging platforms on the market. The Yole Développement quantitative analysis of the market is shown in Figure 1: They offered the comparison slide ... »

IFTLE 408: Plasma Dicing ; Intel compares High-density Packaging for HI

IFTLE 408: Plasma Dicing ; Intel compares High-density Packaging for HI

Plasma Dicing Advanced packaging is bringing with it new ways to separate die from the wafer. In the past, wafer dicing was traditionally carried out using conventional dicing “saw”. However, this method has limitations such as die chipping or cracking leading to lower device yields. Also, the width of the blade removes valuable “real estate” from the wafer. Newer techniques include laser ... »

IFTLE 407: Intel Lakefield Uses 3D Stacking; SEMI Europe’s 3D & System Summit

IFTLE 407: Intel Lakefield Uses 3D Stacking; SEMI Europe’s 3D & System Summit

At CES 2019, Intel previewed a new client platform, code-named “Lakefield”. It featured the first iteration of its new innovative Foveros 3D packaging technology. The Lakefield stacked module will contain: 10nm hybrid CPU architecture Gen 11 graphics Multiple dies stacked on top of each other The die is then stacked using micro-bumps on the active interposer through which through silicon v... »

IFTLE 406: Rumors about GlobalFoundries; TSMC’s $0.5B Resist Mishap; Bridg

IFTLE 406: Rumors about GlobalFoundries; TSMC’s $0.5B Resist Mishap; Bridg

In this post, we interrupt our regularly scheduled conference review to look at some items that should be of interest to us all. Is GlobalFoundries (GF) Up for Sale? GlobalFoundries is currently the 3rd largest semiconductor foundry supplier with a reported 8.4% market share, just behind TSMC and Samsung. It has five 200 mm wafer fabrication plants in Singapore, one 300 mm plant each in Germany an... »

IFTLE 405: DC Hu of SiPlus Classifies Advanced Packaging Technologies at IMPACT 2018

IFTLE 405: DC Hu of SiPlus Classifies Advanced Packaging Technologies at IMPACT 2018

As scientists, we have a tendency to classify and categorize. It’s our way of comparing and contrasting things in our world. Some of these classifications stick and some don’t. For instance at the start of 3D a decade or so ago, Eric Beyne of IMEC laid out a perfectly reasonable classification of 3D structures based on the level of interconnect they were making. [ Link] It made all the sense i... »

IFTLE 404: One Micron RDL; FOWLP Die Shift; Antennas for FOWLP

IFTLE 404: One Micron RDL; FOWLP Die Shift; Antennas for FOWLP

In this IFTLE post, we continue our look at presentations from the 2018 EPTC Conference… Ultratech / IMEC / JSR – 1µm RDL Ultratech, IMEC and JSR discussed “One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging using a Photosensitive Dielectric Material”. This study compared the creation of 1.0μm RDL structures by a damascene process utilizing a photosensitive permanent d... »

IFTLE 403: TSMC 4th Generation CoWoS; 2018 Singapore EPTC Part 1

IFTLE 403: TSMC 4th Generation CoWoS; 2018 Singapore EPTC Part 1

Heterogeneous Integration spurs demand for 3D backend solutions Julian Ho reported in the Jan 10th issue of Digitimes that heterogeneous integration of diverse semiconductor components to support 5G, AI, automotive electronics, and IoT applications is gaining significant momentum, driving demand for system-in-package (SiP) and system-on-3D package (So3D) processes and boosting the importance of c... »

IFTLE 402: Advanced Packaging Underfills; JEDEC Updates HBM Memory Standard; Intel Foundry Business

IFTLE 402: Advanced Packaging Underfills; JEDEC Updates HBM Memory Standard; Intel Foundry Business

Continuing our look at presentations from the recent 2018 IWLPC conference, let’s look at the Jiw Pai Henkel presentation on advanced packaging underfills. Henkel – Underfill Options for Advanced Packaging Bai and co-workers examined the use of capillary underfill (CUF), non-conductive paste (NCP)  and non-conductive film (NCF) in advanced packaging applications (Figures 1 and 2). Each of... »

IFTLE 401: FOWLP for RF; D2W Hybrid Bonding; FOPLP in Samsung Watch

IFTLE 401: FOWLP for RF; D2W Hybrid Bonding; FOPLP in Samsung Watch

As its name implies, the International Wafer Level Packaging Conference (IWLPC) initially covered wafer-level packaging (WLP) technologies. As all conferences do, it soon expanded its scope to cover basically all advanced packaging topics including WLP, fan-out wafer-level packaging (FOWLP), 2.5D/3D, and advanced manufacturing and test, etc. Statistics from this year’s show include: 809 Atte... »

IFTLE 400: Intel Logic-Logic 3DIC and Chiplets are Finally Here

IFTLE 400: Intel Logic-Logic 3DIC and Chiplets are Finally Here

At the Intel “architecture day” held Dec 12th in Santa Clara, Intel finally announced what some of us have been waiting for, literally for over a decade. The Foveros Backstory In late 2006, CEO Paul Otellini displayed a 300mm wafer of 80 core microprocessors (Figure 1) and announced that such technology would soon be in production. In 2007 Bryan Black (later of AMD), Morrow and other Intel res... »

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