Plasma Dicing Advanced packaging is bringing with it new ways to separate die from the wafer. In the past, wafer dicing was traditionally carried out using conventional dicing “saw”. However, this method has limitations such as die chipping or cracking leading to lower device yields. Also, the width of the blade removes valuable “real estate” from the wafer. Newer techniques include laser ... »
At CES 2019, Intel previewed a new client platform, code-named “Lakefield”. It featured the first iteration of its new innovative Foveros 3D packaging technology. The Lakefield stacked module will contain: 10nm hybrid CPU architecture Gen 11 graphics Multiple dies stacked on top of each other The die is then stacked using micro-bumps on the active interposer through which through silicon v... »
In this post, we interrupt our regularly scheduled conference review to look at some items that should be of interest to us all. Is GlobalFoundries (GF) Up for Sale? GlobalFoundries is currently the 3rd largest semiconductor foundry supplier with a reported 8.4% market share, just behind TSMC and Samsung. It has five 200 mm wafer fabrication plants in Singapore, one 300 mm plant each in Germany an... »
As scientists, we have a tendency to classify and categorize. It’s our way of comparing and contrasting things in our world. Some of these classifications stick and some don’t. For instance at the start of 3D a decade or so ago, Eric Beyne of IMEC laid out a perfectly reasonable classification of 3D structures based on the level of interconnect they were making. [ Link] It made all the sense i... »
In this IFTLE post, we continue our look at presentations from the 2018 EPTC Conference… Ultratech / IMEC / JSR – 1µm RDL Ultratech, IMEC and JSR discussed “One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging using a Photosensitive Dielectric Material”. This study compared the creation of 1.0μm RDL structures by a damascene process utilizing a photosensitive permanent d... »
Heterogeneous Integration spurs demand for 3D backend solutions Julian Ho reported in the Jan 10th issue of Digitimes that heterogeneous integration of diverse semiconductor components to support 5G, AI, automotive electronics, and IoT applications is gaining significant momentum, driving demand for system-in-package (SiP) and system-on-3D package (So3D) processes and boosting the importance of c... »
Continuing our look at presentations from the recent 2018 IWLPC conference, let’s look at the Jiw Pai Henkel presentation on advanced packaging underfills. Henkel – Underfill Options for Advanced Packaging Bai and co-workers examined the use of capillary underfill (CUF), non-conductive paste (NCP) and non-conductive film (NCF) in advanced packaging applications (Figures 1 and 2). Each of... »
As its name implies, the International Wafer Level Packaging Conference (IWLPC) initially covered wafer-level packaging (WLP) technologies. As all conferences do, it soon expanded its scope to cover basically all advanced packaging topics including WLP, fan-out wafer-level packaging (FOWLP), 2.5D/3D, and advanced manufacturing and test, etc. Statistics from this year’s show include: 809 Atte... »
At the Intel “architecture day” held Dec 12th in Santa Clara, Intel finally announced what some of us have been waiting for, literally for over a decade. The Foveros Backstory In late 2006, CEO Paul Otellini displayed a 300mm wafer of 80 core microprocessors (Figure 1) and announced that such technology would soon be in production. In 2007 Bryan Black (later of AMD), Morrow and other Intel res... »
Who was Madeline on Halloween? Before we start more tech coverage of IMAPS 2018 with a look at polymer dielectric advancements, long time readers know that you are due a Halloween update on my granddaughters. This year I’m focusing on Madeline who will be eleven in February. Her Halloween disguise this year was from her favorite Netflix TV show. Can you guess the character and the show?? I hav... »
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