Perspectives on the Cost of Fan-out Wafer Level Packaging vs. Flip Chip Packaging

Perspectives on the Cost of Fan-out Wafer Level Packaging vs. Flip Chip Packaging

Recently, I read a paper published in the 2017 IMAPS Device Packaging Conference proceedings, titled “Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging,” written by Amy Lujan, of Savansys. Lujan did a very good analysis on the cost comparison of fan-out wafer-level packaging (FOWLP)  with chip-first and die face-down and flip chip (FC) packaging, according to an activity-based cost (ABC) modeling. Emphasis was placed on the cost comparison to determine which design features drive a design to be packaged more cost-effectively as an FC package, and which design features result in a lower cost FOWLP. A wide range of chip/package sizes has been considered [1].

The purpose of this post based on Lujan’s findings [1] is to focus only on the potential “real” application ranges of FOWLP, i.e., package/chip ratio. The present conclusions are shown at the bottom of all the figures, except Figure 1, from [1].

Analyses

Figure 1 shows the process of the FC packaging and FOWLP.

cost comparison of FOWLP and FC.

Figure 1: Process flows of FOWLP and FC used in the cost comparison. Figure courtesy of Amy Lujan, Savansys, LLC.

Figure 2 shows the processing cost comparison of FC and FOWLP by varying package sizes and considering two chip sizes (5mmx5mm and 3mmx3mm). For both chip sizes, in the application range of FOWLP (package/chip ratio = 3.24 and 4, respectively), the processing cost of FOWLP is lower than that of FC packaging.

Figure 2: For chip size 5mm x 5mm, the FOWLP size is definitely <9mm x 9mm or a 3.24 package/chip ratio. This FOWLP cost less than a flip chip package. For chip size 3mm x 3mm, the FOWLP size is definitely <6mm X 6mm or a 4.0 package/chip ratio. Thus FOWLP cost less than a flip chip package.

Figure 3 shows the processing cost comparison of FC and FOWLP by varying chip sizes and considering one package size (13mmx13mm). It can be seen that, in the application range of FOWLP (package/chip ratio = 2.64), the processing cost of FOWLP is lower than that of a FC package.

Figure 3: Looking at varying die sizes including only process cost. For 13mm x 13mm FOWLP, the chip size is definitely greater than 8mm x 8mm or a 2.64 package/chip ratio. Thus the FOWLP cost less than a flip chip package.

Figure 4 shows the processing + die cost comparison of FC and FOWLP by varying chip sizes and considering two die costs ($1 and $2). The package size = 13mmx13mm. It can be seen that, in the application range of FOWLP (package/chip ratio = 2.64), the processing cost (with the die cost included) of FOWLP is lower than that of FC package.

Figure 4: Comparison of varying die sizes, die cost included. For FOWLP size 13mm x 13mm, the chip size is definitely > 8mm x 8mm or a 2.64 package/chip ratio. Thus the FOWLP cost less than a flip chip package.

Figure 5 shows the processing cost + yield comparison of FC and FOWLP by varying package sizes and considering two die costs ($1 and $2). The chip size = 3mmx3mm. It can be seen that, in the application range of FOWLP (package/chip ratio = 2.8), even with all the yield loss considered for FOWLP, the processing cost (with the die cost included) of FOWLP is cheaper than that of FC package. For the definition of processing yield, please read [1].

Figure 5: Based on a yield comparison of varying packages, for a 3mm x 3mm chip, the FOWLP size is <5mm x 5mm or a package/chip ratio of 2.8. Thus even with all the yield loss considered for FOWLP, it is still a lower cost option than a flip chip package.

Figure 6 shows the processing cost + yield comparison of FC and FOWLP by varying chip sizes and considering two die costs ($1 and $2). The package size = 13mmx13mm. It can be seen that, in the application range of FOWLP (package/chip ratio = 2.34), even with all the yield loss considered for FOWLP, the processing cost (with the die cost included) of FOWLP is lower than that of FC package.

Figure 6: For varying die size based on yield comparison, for a 13mm x 3mm FOWLP, the chip size is > 8.5mm x 8.5mm or a package/chip ratio of 2.34. Thus, even with all the yield loss considered for FOWLP, it’s still a lower cost option than a flip chip package.

Summary

Some important results are summarized as follows:

  • Based on Lujan’s ABC modeling and findings [1], and focus on the application ranges of FOWLP, i.e., package/chip ratio, some useful conclusions have been obtained.
  • For all the cases considered, the cost of FOWLP is lower than that of FC packaging.

Reference

[1]    Lujan, A. P., “Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging”, IMAPS 2017, pp. 1-5.

For other reading on this topic, see the Amy Lujan’s 3D InCites post, also based on her paper.