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The constant demand for miniaturization, added functionality and increased performance of electronic devices systematically drives higher integration by adding more devices on a single chip. In addition, 3-D or 2.5-D packaging, require on-chip or in-package capacitors, not only in traditional integrated circuits but also for integrated components, possibly on interposers, such as decoupling capaci... »
Fan-out wafer-level packaging (FOWLP) is a cost-effective way to achieve high interconnect density and to manage larger I/O counts within an affordable package. It enables smaller footprints, higher interconnect density, better routing and thinner packages than current technologies. [1] A standard FOWLP wafer comprises known good die (KGD) and a redistribution layer (RDL) or layers embedded in mol... »
Stacking chips on top of each other (aka 3D stacking) is a well-known approach to make more compact and powerful systems. Until now, it was impossible to probe the large arrays of fine-pitch micro-bumps on advanced chips before stacking. This had a negative effect on the compound yield (because of including faulty dies in the stack). Imec, together with FormFactor (formerly Cascade Microtech), has... »
In recent years, the technology of 3D integration has evolved into an economically interesting road. In particular, the technology is used to package the CMOS imagers you find in your smartphone, the high-bandwidth DRAM memory stacks used in high-end computing, as well as in advanced graphics cards. 3D integration allows a significant reduction of a system’s footprint and enables ever shorter an... »
Data is now the world’s most valuable resource. Solid-state storage of data is driving an innovation revolution built upon 50 years of progress. Here we look at the dual-gate thin film transistor (DG-TFT), an extremely versatile solid-state data storage device that can be used in monolithic 3D as either a flash memory or a dynamic memory element. It has the potential to provide a path not only ... »
More and more applications are calling for miniaturized electronics to integrate high-performance devices in a limited volume. 3D technology is being driven by the consumer markets as smartphones, tablets and many handheld devices require advanced features in light and thin products. Currently, those requirements are being fulfilled by fan-in or package on package (PoP) technologies, but real 3D l... »
In recent years, there has been an increased focus on fan-out wafer level packaging. While fan-out wafer level packaging may be the right solution for some designs, it is not always the lowest cost solution. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. Both technologies are suitable for many of the same applications, and it is impo... »
Organic paper, particularly cellulose-based paper, efficiently served in previous eras as an engineering material. In the Tang dynasty, soldier armors were mainly made of paper [57]. In the era of analog computing, paper volvelles [18] were used, in particular, in the calculation of physical phenomena. The E6-B flight computer is a paper volvelle that was used by pilots to determine, for instance,... »
A little over a year ago, I wrote a Knowledge Portal entry about the cost of 3D ICs. Here I am again to tackle the issue of 2.5D and 3D cost reduction from a slightly different angle. This entry is based on what SavanSys presented at IMAPS Device Packaging 2016. The previous Knowledge Portal entry spent time discussing cost drivers; a few specific numbers were provided, but overall, the details we... »
Through silicon via (TSV) technology is a key design element being incorporated into more and more advanced packaging designs today. TSVs offer distinct benefits in form factor and improved performance and can enable new, innovative designs not previously possible. To scale this valuable technology and spark industry adoption, there is a need to refine and optimize the TSV reveal process to reduce... »
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