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Part 4 of the series, The Triumph of Quantum Mechanics at the Heart of Solid-State Data Storage, continues with the future of non-volatile memory. The figure above is a concept for 3D stacking of Flash devices. A thin-film field effect transistor with a silicon nitride as charge reservoir and a tunnel oxide. A.J. Walker et al., VLSI Symposium, 2003. The relentless shrinking of NAND Flash from ... »
Part 3 of the series, The Triumph of Quantum Mechanics at the Heart of Solid-State Data Storage, continues with the invention of NAND flash memory. The above image is of the first comprehensive paper reporting the NAND Flash invention where Fowler-Nordheim tunneling is used for program and erase of the memory. [1] After the fundamental studies in the late 1960’s Quantum Mechanical tunneling... »
Part 2 of the series, The Triumph of Quantum Mechanics at the Heart of Solid-State Data Storage, continues with a history lesson on the invention of tunneling-based flash memory. In 1956, William Shockley, shared the Nobel Prize in physics with J. Bardeen and W.H. Brattain, all at Bell Laboratories, “for their researches on semiconductors and their discovery of the transistor effect”. T... »
The mid-1920’s were the miracle years for quantum mechanics. The “Old Quantum Theory” originating with Niels Bohr, had reached crisis point by the end of 1924. Wave-particle duality from Einstein and de Broglie called for something new. The great theorists, Heisenberg, Born, Jordan, Schrödinger, and Dirac, published different formulations of a new theory that were quickly shown... »
If all the data sent worldwide each day on the internet were burned on to CDs and these were then piled one on top of the other, the resulting heap would reach Mars and back again. Much of this data is thankfully not stored on CDs but rather in much more efficient solid-state memories. And at the heart of these is fascinating, some would say weird, fundamental physics that explains a myr... »
The constant demand for miniaturization, added functionality and increased performance of electronic devices systematically drives higher integration by adding more devices on a single chip. In addition, 3-D or 2.5-D packaging, require on-chip or in-package capacitors, not only in traditional integrated circuits but also for integrated components, possibly on interposers, such as decoupling capaci... »
Fan-out wafer-level packaging (FOWLP) is a cost-effective way to achieve high interconnect density and to manage larger I/O counts within an affordable package. It enables smaller footprints, higher interconnect density, better routing and thinner packages than current technologies. [1] A standard FOWLP wafer comprises known good die (KGD) and a redistribution layer (RDL) or layers embedded in mol... »
Stacking chips on top of each other (aka 3D stacking) is a well-known approach to make more compact and powerful systems. Until now, it was impossible to probe the large arrays of fine-pitch micro-bumps on advanced chips before stacking. This had a negative effect on the compound yield (because of including faulty dies in the stack). Imec, together with FormFactor (formerly Cascade Microtech), has... »
In recent years, the technology of 3D integration has evolved into an economically interesting road. In particular, the technology is used to package the CMOS imagers you find in your smartphone, the high-bandwidth DRAM memory stacks used in high-end computing, as well as in advanced graphics cards. 3D integration allows a significant reduction of a system’s footprint and enables ever shorter an... »
Data is now the world’s most valuable resource. Solid-state storage of data is driving an innovation revolution built upon 50 years of progress. Here we look at the dual-gate thin film transistor (DG-TFT), an extremely versatile solid-state data storage device that can be used in monolithic 3D as either a flash memory or a dynamic memory element. It has the potential to provide a path not only ... »
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