Technologies Features

3D Systems-on-Chip: Clever Circuit Partitioning To Extend Moore’s Law

3D Systems-on-Chip: Clever Circuit Partitioning To Extend Moore’s Law

In recent years, the technology of 3D integration has evolved into an economically interesting road. In particular, the technology is used to package the CMOS imagers you find in your smartphone, the high-bandwidth DRAM memory stacks used in high-end computing, as well as in advanced graphics cards. 3D integration allows a significant reduction of a system’s footprint and enables ever shorter an... »

The Dual-Gate Thin Film Transistor for 3D Dynamic and Flash Memory

The Dual-Gate Thin Film Transistor for 3D Dynamic and Flash Memory

Data is now the world’s most valuable resource. Solid-state storage of data is driving an innovation revolution built upon 50 years of progress. Here we look at the dual-gate thin film transistor (DG-TFT), an extremely versatile solid-state data storage device that can be used in monolithic 3D as either a flash memory or a dynamic memory element. It has the potential to provide a path not only ... »

Wire-free Die-on-die Technology for Electronic Module Manufacturing in Implantable Devices

Wire-free Die-on-die Technology for Electronic Module Manufacturing in Implantable Devices

More and more applications are calling for miniaturized electronics to integrate high-performance devices in a limited volume. 3D technology is being driven by the consumer markets as smartphones, tablets and many handheld devices require advanced features in light and thin products. Currently, those requirements are being fulfilled by fan-in or package on package (PoP) technologies, but real 3D l... »

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

In recent years, there has been an increased focus on fan-out wafer level packaging. While fan-out wafer level packaging may be the right solution for some designs, it is not always the lowest cost solution. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. Both technologies are suitable for many of the same applications, and it is impo... »

Reinventing Paper for Electronics and 3D Technology

Reinventing Paper for Electronics and 3D Technology

Organic paper, particularly cellulose-based paper, efficiently served in previous eras as an engineering material. In the Tang dynasty, soldier armors were mainly made of paper [57]. In the era of analog computing, paper volvelles [18] were used, in particular, in the calculation of physical phenomena. The E6-B flight computer is a paper volvelle that was used by pilots to determine, for instance,... »

Opportunities for 2.5D and 3D Cost Reduction

Opportunities for 2.5D and 3D Cost Reduction

A little over a year ago, I wrote a Knowledge Portal entry about the cost of 3D ICs. Here I am again to tackle the issue of 2.5D and 3D cost reduction from a slightly different angle. This entry is based on what SavanSys presented at IMAPS Device Packaging 2016. The previous Knowledge Portal entry spent time discussing cost drivers; a few specific numbers were provided, but overall, the details we... »

Cost Analysis of a Wet Etch TSV Reveal Process

Cost Analysis of a Wet Etch TSV Reveal Process

Through silicon via (TSV) technology is a key design element being incorporated into more and more advanced packaging designs today. TSVs offer distinct benefits in form factor and improved performance and can enable new, innovative designs not previously possible. To scale this valuable technology and spark industry adoption, there is a need to refine and optimize the TSV reveal process to reduce... »

Fraunhofer EMFT: Our Early and Ongoing Work in 3D Integration

Fraunhofer EMFT: Our Early and Ongoing Work in 3D Integration

Fraunhofer has been working on 3D integration for the past three decades, starting in1987 with a consortium of Siemens, AEG, Philips and the Munich institute IFT (now EMFT).  By 1988, we could successfully fabricate 3D CMOS devices based on recrystallization of deposited poly-Si. In the mid-1990s, we developed a complete process flow for “Through-Si Via technology (TSV) in close cooperation ... »

The Commercialization of 3D Stackable Memory – Part Two

The Commercialization of 3D Stackable Memory – Part Two

The Opportunities for RRAM Cells to Take 3D Stackable Memory to 8-nm Nodes In Part One of this two-part series, we looked at the challenges that need to be overcome in manufacturing 3D stackable memory using the competing technology approaches. We will now focus on the advantages inherent in resistive memory technology over current NAND technology in taking 3D memory on a familiar and reasonable ... »

The Commercialization of 3D Stackable Memory: Part One

The Commercialization of 3D Stackable Memory: Part One

The Challenges of Manufacturing 3D Stackable Memory Memory technologies vying to fulfill the increasing capacity and density requirements of the solid-state storage market two years from now will be confronted by having to meet demanding cell performance and cost-per-bit metrics to be viable. Today, NAND technology is still the primary solution for building solid-state storage devices (SSD), as th... »

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