System-technology co-optimization (STCO) – enabled by 3D integration technologies – is seen as a next ‘knob’ for continuing the scaling path. Eric Beyne, imec fellow and program director of imec’s 3D system integration program and Julien Ryckaert, program director 3D hybrid scaling at imec, unravel the STCO principle, open up the 3D technology toolbox and bring up two promising cases: lo... »
When I joined imec in October 2008 to work on test and design- for- test (DfT) of 3D-stacked integrated circuits (ICs), there were only a few test folks active in that emerging field. Consequently, misconceptions about 3D test were omnipresent. In the November 18, 2008 issue of Semiconductor International, Alexander Braun wrote: “At a symposium yesterday on 3-D integration, leading expert Philip... »
The expected increase of the power device market, with a compound annual growth rate (CAGR) of more than 10% — and more particularly insulated-gate bipolar transistor (IGBT) products for automotive and other applications — is pushing the semiconductor industry to adopt specific process solutions. The maturity of IGBT market, boosted by booming demand for electrified vehicles (EV) and hybrid el... »
Almost four years ago, we published an article titled “CoolCube™: A True 3DVLSI Alternative to Scaling” on 3D InCites. It described the concept of stacking layers of transistors sequentially on top of each other and documented the research effort happening at Leti to develop a feasible process integration scheme and a comprehensive product design frame. Now, four years later, we can say that... »
NMP is an abbreviation for N-methyl-2-pyrrolidone (other synonyms are 1-Methyl-2-pyrrolidone and 1-Methyl-2-pyrrolidinone) (Figure 1). NMP has proven itself as an effective and versatile cleaning agent, removing photoresist residue while leaving the surface in good shape for processing steps downstream. However, its time may be short-lived as companies strive to meet environmental health and safet... »
Recently, I read a paper published in the 2017 IMAPS Device Packaging Conference proceedings, titled “Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging,” written by Amy Lujan, of Savansys. Lujan did a very good analysis on the cost comparison of fan-out wafer-level packaging (FOWLP) with chip-first and die face-down and flip chip (FC) packaging, according to a... »
The growing digitalization of our society has made our lives connected and, in many aspects, easier. But the digital revolution also implies that the total amount of data processed in the world is doubling every two years or so. Electronic devices such as mobile phones, laptops, satellites, servers or self-driving vehicles must cope with twice as much data, at higher speeds. Traditional signaling ... »
Part 4 of the series, The Triumph of Quantum Mechanics at the Heart of Solid-State Data Storage, continues with the future of non-volatile memory. The figure above is a concept for 3D stacking of Flash devices. A thin-film field effect transistor with a silicon nitride as charge reservoir and a tunnel oxide. A.J. Walker et al., VLSI Symposium, 2003. The relentless shrinking of NAND Flash from ... »
Part 3 of the series, The Triumph of Quantum Mechanics at the Heart of Solid-State Data Storage, continues with the invention of NAND flash memory. The above image is of the first comprehensive paper reporting the NAND Flash invention where Fowler-Nordheim tunneling is used for program and erase of the memory. [1] After the fundamental studies in the late 1960’s Quantum Mechanical tunneling... »
Part 2 of the series, The Triumph of Quantum Mechanics at the Heart of Solid-State Data Storage, continues with a history lesson on the invention of tunneling-based flash memory. In 1956, William Shockley, shared the Nobel Prize in physics with J. Bardeen and W.H. Brattain, all at Bell Laboratories, “for their researches on semiconductors and their discovery of the transistor effect”. T... »
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