In Part 1 of this article series, we noted that despite the potential benefits associated with 3D and interposer-based 2.5D designs, the incorporation of TSVs poses significant challenges to the performance and reliability of 3D wafer level packages (3D WLP). Among these is the generation of TSV stress in 2.5D/3D packaging – both thermal-induced stress resulting from the coefficient of thermal expansion (CTE) mismatch between the interconnect metal and the silicon substrate, as well as additional stress buildup generated by TSV fabrication.
We also provided an overview on recent tool developments from EV Group to address these issues, including the EVG®150XT resist coating and developing system, which applies photoresist and other functional polymers at and within TSV geometries to act as a stress buffer between the silicon and copper. Used in conjunction with the novel EVG®NanoFill™ process, this solution can create passivation layers that not only protect against corrosion, but also enable isolation to reduce electrical noise, as well as create compliant layers to mitigate thermal stress and permanent passivation of the interconnect. We demonstrated how the EVG150 XT with NanoSpray™ technology can provide highly conformal coating of deep vias, which in turn have demonstrated device electrical improvements.
Now, we will review a two-part case study on improving the thermo-mechanical reliability of TSVs using EVG’s NanoSpray and NanoFill polymer-insulating TSV technologies.
Use Case: Improving Thermo-mechanical Reliability of TSV Interconnects
The advantages of polymer-insulating TSV technology, such as EVG’s NanoSpray technology, are demonstrated by finite element analysis (FEA) simulations. FEA is used to investigate the effect of thermal-induced stress on TSV geometries under elevated temperature conditions. The first example study describes and analyzes the thermo-mechanical behavior of a fully metal-filled TSV structure with a via diameter of 50µm and via depth of 150µm (Figure 1, top left).
The thermal-induced stress is simulated at a moderately elevated temperature of 100°C. As shown in Figure 1 (top middle and right), the high-stress-level concentration at the via-metal interface is clearly visible. FEA results show not only significant thermal-induced stress at the sidewall, but also highly concentrated shear stress and tensile normal stress at TSV corners. These peaks in the stress map indicate locations with high risk of interface de-bonding that can cause TSV pop-up and silicon cracking during repeated heating and cooling cycles. These near-surface stresses also cause degradation of carrier mobility and device performance and thus require KOZs around TSVs to avoid interference with the integrity of adjacent functionalities.
Next, the identical TSV structure is provided with an intermediate (5µm) layer of benzocyclobutene (BCB) based polymer (Figure 1, bottom left), which can be applied using EVG’s NanoSpray technology. Because of the familiarity with the material and widespread processing capabilities, BCB-based polymer is used to demonstrate the functionality of the annular polymer-lining concept for this study. The thermal and dielectric performances of BCB-based materials show low dielectric property with a dielectric constant below 2.64. Moreover, new BCB-based materials show higher thermal stability (T0 ≤ 427°C, T5% ≤ 552°C) and can be considered as potential candidates for permanent TSV liners.
The FEA results of thermal stress for fully-filled copper TSVs with BCB liner with identical dimensions under the same temperature conditions show significant relaxation of stress levels around the TSV structure. In particular, the interfacial region between copper and silicon shows a marked decrease in thermal-induced stress (Figure 1, bottom middle and right). As a positive consequence, the area of KOZ can be significantly reduced using an annular TSV structure, thereby allowing denser packing of TSVs with no parasitic cross-effects. Experimental techniques, test structures and metrology for accurately measuring the stress at TSV interfaces have to be developed in order to determine accurate values for TSV reliability.
The extent of thermally induced stress strongly correlates to the metal filling used to fabricate the TSV. Several metals, such as copper, tungsten, and nickel, are being considered for use in 3D TSVs. The difference in thermo-mechanical reliability among these materials is of interest, since a metal with a low modulus and a low CTE is favored for reducing the driving force for delamination. Unfortunately, a metal with low modulus usually comes with a high CTE, and vice versa. The thermo-mechanical properties of four commonly used metals and for silicon are listed in Table 1.
The driving force for TSV delamination significantly decreases with reduced CTE of the metal, as a square function of the CTE mismatch between the metal and the silicon matrix. Given the same thermal load and TSV dimension, tungsten, which has the lowest CTE among the four materials, exhibits the least force for delamination. However, the interfacial adhesion between the metallization material and the barrier layer of TSVs also plays an important role in controlling delamination. In this case, copper can develop more plastic deformation compared to tungsten. Therefore, copper can absorb energy by plastic deformation near the crack tip and increase the fracture resistance to crack propagation. Ultimately, the advantage of tungsten over copper is balanced by its brittleness and the lack of plasticity in deformation.
The second part of this study focuses on the investigation of the thermo-mechanical behavior of a TSV interconnect design using annular metal contacts instead of full metal fillings. To ensure the comparability of the investigations, identical TSV geometries were used for the second part of this study, with a via diameter of 50µm and via depth of 150µm (Figure 2, top left). In reviewing the FEA simulation results for this second TSV design under thermal induced stress at a moderately elevated temperature (100°C), the changed stress distribution within the TSV is clearly visible (Figure 2, top middle and right). Reduced stress concentration is observed along the via-metal interface within the TSV geometry. However, the punctual stress load at the top edges is still sufficiently high to cause delamination and extrusion of the filling. The results also reveal significantly increased mechanical stress directed toward the inside of the hollow metal contact. This is due to the sheer lack of mechanical support to the inside of the metal structure. Ultimately, the annular TSV design shows improved stress characteristics along the via sidewalls, but it shifts the problem elsewhere rather than solves it.
A significant relaxation of the overall stress map of the hollow TSV structure is observed when the identical TSV structure is provided with an intermediate (5µm) layer of BCB (Figure 2, bottom left). As in the previous polymer insulating example, the relaxation due to the insertion of the annular polymer interlayer is most pronounced along the interfacial region. Nonetheless, a significant reduction of stress is observed in the interior of the hollow structure as well (Figure 2, bottom middle and right).
Filling up the open via with polymer to seal the metallization from atmospheric influences and downstream processes can further improve thermo-mechanical behavior, and thus, the electrical reliability of this 3D interconnect. However, using a standard spin coat technique to fill and planarize very deep trenches and high-aspect-ratio structures has many limitations and usually results in voids of trapped air within the polymer filling, non-planar topographies, and lack of polymer flow to the requisite depths. To overcome this issue, EVG’s NanoFill technique can be applied, which completely fills and planarizes the open TSV structure with polymeric material without voids or cavities within the polymer (Figure 3).
TSV interconnects are critical to the development of 2.5D/3D-ICs since they enable through-chip communication between the vertically stacked device layers. Photoresist processing and lithography for MEOL processes, in turn, are increasingly critical for 3D integration concepts and 3D-WLP. For example, resist coating layers are needed around the sidewalls of TSVs—for passivation to protect against corrosion, isolation to reduce electrical noise, as a compliant layer to mitigate thermal stress or as a photoresist mask for in-via photolithography prior to etching. Successfully entering this new era requires new advancements in wafer processing equipment dedicated to 3D WLP, particularly in the areas of improved processing, shorter cycle times, and complex, high-frequency process flows. The EVG150 XT system in conjunction with NanoSpray and NanoFill technologies addresses the production needs for MEOL and BEOL lithography, conformal coating, passivation and planarization in a modular, fully automated resist processing tool that supports wafers up to 300mm in diameter and is optimized for high throughput and maximum productivity.