To satisfy industry demand for continued increases in electronic functions per unit area, foundries and outsourced assembly and test (OSAT) companies have shifted their emphasis to driving advanced IC packaging innovation. One path is to integrate, in the package, smaller, heterogeneous, or homogeneous, high-yield chips or chiplets: functional building blocks that when combined provide the same capabilities as a monolithic system on chip (SoC).
Several leading foundries and OSATs already offer such high-density advanced packaging (HDAP) services to their customers. The most common of these advanced IC packaging technologies are interposer-based 2.5D-ICs and single or multi-die fan-out wafer-level packaging (FO-WLP), as shown in Figure 1. These new package types use new materials and processes that are often more similar to silicon wafer fab processes than to traditional organic package substrate processes.
Unfortunately, companies adopting these advanced IC packaging technologies often fail to recognize that their legacy approaches to component-level verification do not scale to multi-die, multi-substrate heterogeneous assemblies and, therefore, can result in low yields. Automated layout versus schematic (LVS) checking is not historically popular in the packaging world because the number of components and required I/Os is usually small, so a simple spreadsheet or bonding diagram is sufficient for an eyeball check. However, as HDAP evolves and its use expands, the need for an automated LVS-like flow to detect and highlight package connectivity errors has become apparent.
In this paper, we will look at some of the most common package verification issues and how designers can resolve them using the Calibre® 3DSTACK™ tool with automated package LVS capabilities.