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The challenge of designing smaller, cost-effective systems that require additional processing and performance power led to 3D chip stacking of bare die and a new approach to packaging known as SiP (systems-in-package), also known as multi-chip modules (MCMs). The benefits of MCM/SiP package technology include the ability to achieve greater functionality in a reduced time-to-market window that cann... »
At this year’s International Wafer-level Packaging Conference, almost 1000 semiconductor experts from all parts of the supply chain gathered at the DoubleTree Hotel in San Jose from October 23 to 25. Among them were also several electronic design automation (EDA) experts who discussed how to streamline die-package-board co-design. They explained how EDA tools enable higher performance per Watt a... »
This year’s Design Automation Conference (DAC 2018) was held at Moscone West, San Francisco, CA. On three levels, about 175 exhibitors showed their capabilities and discussed market needs. Our industry’s focus on artificial intelligence (AI) and machine learning (ML) solutions were clearly obvious, and I suspect, attracted more young people and a fairly large number of new exhibitors to DAC th... »
Editor’s note: For several years now, Mentor Graphics has evangelized about the critical need for assembly design kits to enable commercialization of high-density advanced packaging technologies, such as fine line and space fan-out, 2.5D and 3D IC packages. With this week’s introduction of a unique, end-to-end, high-density advanced packaging (HDAP) design flow, combined with the launch of an... »
In the past, the Design Automation Conference was known to me and many of my colleagues as the annual event that focused on IC design tools, flows, and methodologies. EDA tools vendors and users got together in the previous millennium to discuss what to do next in a rapidly growing market segment. Then things changed… At the beginning of this millennium, the wafer foundries took charge of silic... »
It is often claimed that 3D chip stacks offer the potential to meet current and future requirements of digital circuits, such as for performance, functionality, and power consumption. Specifically, both design paradigms “More Moore” and “More than Moore” will benefit from 3D chip stacking (and new technologies and materials). 3D stacking enables notably reduced interconnect... »
DesignCon 2016 at the Santa Clara Convention Center gave football fans among us an opportunity to watch the preparation work for Super Bowl 50. Right across the street from the Convention Center is Levi Stadium, where on Sunday, February 7, this year’s champion will be crowned. Impressive, but let’s not digress and focus on DesignCon. For me, in my role as business developer for innovative pro... »
A few weeks ago, San Francisco’s Moscone Center hosted the Design Automation Conference (DAC 2015), with many EDA experts and their customers focused on how to design the new wave of 10nm chips, this year and next. Last week the Moscone Center was buzzing again, this time with material suppliers, equipment vendors, and IC manufacturing experts, discussing how to ramp up production and improve yi... »
By attracting 7011 EDA and IP developers and users, the 52 Design Automation Conference, held in the South Hall of San Francisco’s Moscone Center in the week of June 7, achieved a 14.5% increase in attendees. I was one of them, and started on Sunday evening by listening to Gary Smith’ EDA Forecast presentation. Based on Gary’s and Laurie Blach’s analysis, EDA is likely to grow by 11.2 % ... »
There’s no doubt left in the minds of semiconductor device manufacturers that the processes required to build interposer-based and 3D IC devices are matured and ready for production. However, the jury is still out in the design community because designing 3D ICs still poses a challenge. Si2 has set out to change that and bring confidence to the minds of chip and system-level designers. Steve Sc... »
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