When 3D is 3D IC, and When it’s Not

Some of the best news to read (especially on a Friday) is non-news, like this report by Ann Steffora Mutschler, in SemiMD on how 3D ICs will not impact computational lithography tools. According to her sources, this particularly true with regards to TSVs, because of their large size in comparison with feature sizes lithography tools are used to dealing with when fabricating 3D transistors or FinFETS.

This article gets a little confusing when Mutschler “switches gears” to discuss “3D devices,” which also seem to be a non-issue with computational lithography. It’s important to be careful when combining an article on 3D ICs and 3D transistors because the manufacturing processes are not the same, and you might as well compare apples to oranges. 3D ICs refers to stacking die, and interconnecting them with through silicon vias (TSVs). 3D transistors are fabricated at (you guessed it) the transistor level, and involves fabricating 3D features on the transistor gates themselves.  Anyway, in this case, no news is good news.

And speaking of non-3DIC  3D technologies, SemiMD’s Mark Lepedus posted a comprehensive article titled What’s After NAND Flash?, which I read because I’m trying to learn more about monolithic 3D; and I’m told the memory space is where I should go to find that. In this post, LePedus compares the 3 possible replacements for existing NAND in the next generation, namely scaling existing NAND, 3D NAND, and other memory types in development at companies like Toshiba and SanDisk. He says ‘the initial and most promising successor is 3D NAND, and some of his sources predict production as soon as 2013 while others point to 2015. He goes in to detail on the process steps (in comparison with stacking 3D DRAM on logic) as well as outlining other competing technologies and the ongoing debates.

In the strictly 3D IC stacking space, I came across a reality check “Experts at the Table” discussion this week on SemiMD (It sure is a SemiMD day today on 3D InCites – I swear I did not plan it this way), in which Ed Sperling tasks industry execs from across the value chain with the hard questions about what’s holding back 3D IC commercialization.

Not surprisingly, the responses are varied in their optimism, reflecting the ongoing debate on this topic. Manish Ranjan (Ultratech) points to customer reluctance to commit, the as yet unsolved “supply chain” issues, and the lack of tools to handle the thermal issues for integrating memory and logic. On the other hand, Thorsten Matthias (EV Group) calls the future “very bright” for 3D ICs, and recalls how far we’ve come proving manufacturability and developing the processes. He says “there are no unsolved issues in manufacturing”, and now its just about making them “smarter.” GlobalFoundries’ Patel agrees, and says its all about maturity, and that the industry needs to work through the supply chain. His recommendation? “We (foundries) need to do the front-end and hand it off to the OSATs, who are experts in handling the wafer thinning and backside processing.” Scott Smith (Synopsys) offered the EDA perspective, noting that he sees all parts of the ecosystem doing their part, including the EDA vendors. Steve Pateras (Mentor Graphics) talked about both the progress and remaining issues with test and the needs for standards. And at the end of the day, it still comes down to as Ranjan calls it a “cost-to-performance” issue, and that the costs have yet to be characterized. He doesn’t see true 3D taking off until 14nm.

Here’s what I think. If we take a good look at the system cost savings for integrating 3D ICs from a value chain perspective versus a supply chain perspective, the “cost-to-performance” issue would be clear, and remaining snags would rapidly be addressed and disappear. ~ F.v.T