After seeing the latest press release on Ziptronix foray into the memory space, I sought out Kathy Cook, business development manager at Ziptronix, at ECTC to get the full story. We’ve been reading and hearing a lot about Ziptronix ZiBond process being used in CMOS image sensor (BSI) technology, and particularly in its recent partnership with Sony for CIS with backside illumination (BSI). ZiBond is the name of the company’s patented room temperature direct oxide bond technology. The latest announcement involves the company’s second product, direct bond interconnect (DBI), which is an extension of the ZiBond process that forms actual interconnects between die with or without through silicon vias (TSVs).
The press release essentially announced that the company is in collaboration with a new customer to extend the DBI technology to 3D memory applications. While Cook could not disclose the customer, she said that what’s most exciting about this news is not just that the company is working with a customer outside the image space; they’ve done that before, but that the work being done now is with a customer IN the memory space. “We’ve known for a long time that there are applications outside the image sensor space,” explained Cook, “But just us knowing that, and having things start to happen are two different things.”
While memory has long been a compelling application for 3D stacking, it has been plagued by high costs and challenges of die thinning, handling of the thinned dies, and development of reliable interconnect processes. DBI addresses both of these issues. The company claims that through this latest customer collaboration, it is demonstrating cost reduction for server and portable memory applications. And because DBI reportedly creates extremely strong low-stress bonds, it allows wafers to be processed and thinned after bonding, greatly simplifying process requirements by eliminating the need to handle thinned wafers and/or dies. It is also fully compatible with damascene interconnect processing, opening new avenues for foundry-based through-silicon via process flows.
Cook went on to explain the benefits of the DBI process for 3D memory. First of all, is DBI’s scalability. “One thing DBI can do is replace bump technologies when the scalability runs out,” she said. “You wouldn’t use it if you can use bumps.” Additionally, any time you’re making connection with bumps, you’re limited with connectivity across the wafer. In DBI, the connection is made across the entire surface of the wafer rather than just at the bump’s surface. The result is a bonded wafer pair that can withstand a lot more post-bond processing. But the real reason people would move to DBI is when the bumps aren’t small enough, said Cook.
How does it work? In the memory application, DBI replaces standard die-stacking methods. Cook says DBI can be performed with wafers without going through the passivation and extra protection layers. While the pads are still showing, the wafers are bonded together. Initially directed for use in wafer-to-wafer (W2W) bonding, DBI can also be performed die-to-wafer (D2W). “But if you can do it wafer to wafer, why do it any other way?” asked Cook.
One of the issues that drives people to use the slower process of die-to-wafer bonding is the need to use Known Good Die (KGD) for achieving high yields. However, Cook said that she’s noticed customers are making more progress in W2W, particularly with recent developments in built-in self test and repair, which adds significant redundancy, the KGD dilemma is reduced. This is good news as being able to use W2W processes results in exponentially faster throughput.
This latest customer collaboration effort is now moving into the prototype evaluation stage. The company has high hopes for DBI across the 3D spectrum of applications, and if all goes as planned, we can expect to hear announcements of more licensing agreements beyond CIS as the year progresses.