Image Courtesy of TSMC Ltd.

Did you know that when foundries talk about 14nm and 16nm node chips, these devices are in reality no denser than their 20nm predecessors? Or that a particular node name does not reflect the size of any particular chip feature, as it once did? Or that since 2007, the doubling of transistors on a chip has actually been more like 1.6x the number of the previous generation? According to a recent feature article published in the IEEE Spectrum titled, The Status of Moore’s Law: It’s Complicated by Rachel Courtland, node names no longer mean what they used to. Courtland quotes Chenming Hu, the co-inventor of the FinFET as commenting, “Nobody knows anymore what 16nm means or what 14nm means.” In addition to being written for the commoner, I found this article to be quite an eye-opener with regards to what is really happening to scaling, versus how its being spun by marketers “to hide widening technological gaps between chip companies.”


3D InCites has been following developments in temporary bonding/debonding for years, as it’s been an ongoing challenge and bottleneck for commercialization of 3D TSVs. Issues have mostly focused on defects caused be debonding – voids, delamination and cracking – and work being done in materials development to overcome this. This recent article by Jeff Chappell in Semiconductor Engineering offers some additional insight on other concerns with TB/DB, such as throughput. Chappell writes, according to Mark Stromberg, Gartner, “Current systems on the market can manage throughputs of 20 to 25 wafers per hour. Compared to other fab-line tools with a typical throughput of some 60 wafers per hour, that’s a bottleneck in terms of high volume production.” Adding multiple tools to the fab line to address this adds cost. Adding additional modules to existing systems is one way to increase throughput. (EV Group is the only company of note that has introduced a temporary bond/debond system designed for high volume manufacturing, in its XTFrame.) Chappell also talks about the latest material challenge; adhesives with thermal characteristics that can withstand temperatures required for chemical vapor deposition (CVD) and physical vapor deposition (PVD).


The Hybrid Memory Cube continues to draw attention from industry publications. This week, iMicronews covered HMC in its “A Closer Look” series. In addition to the usual overview we’ve come to expect from HMC posts, this one goes into detail on the device structure itself – as much as available information allows, at least. For example, now we know that IBM manufactures the logic layer on 300mm wafers using 32nm technology, and the 30nm DRAM layers are manufactured by Micron. The cube will be assembled by Micron at its Boise location, according to this post. The details of the memory assembly are also included: 50µm thin assembled with 20µm high Cu pillars. The TSV diameter hasn’t been revealed yet, but speculation is 6-7µm based on a presentation from the 2012 VLSI Conference. Details are in the full post. ~ F.v.T.


Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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