In my last blog posting I went over the cost aspects of the Samsung-Toshiba 3D NAND approaches. The conclusion is quite stark: if those vertical holes and trenches are more than a few tenths of a degree from the vertical, then the whole approach can be undercut in cost by more lithography-intensive layered approaches. At the risk of belaboring that point, see the IEEE paper published this month.
Now, I’d like to start looking at some of the technical challenges associated with these 3D NAND approaches. There are several that I’d like to go into so I’ll take a few blog posts to look at each in detail. As with anything, there are various layers of complexity. Here, I’ll keep it at a level where someone without previous semiconductor device experience can follow the flow of events. For anyone with a thirst for a deeper understanding, I’ll include links to more physics-based articles.
To kick things off, I’ll delve into the 3D NAND string current. It may not sound exciting but it turns out its behavior is rather unique in the vertical channel 3D NAND approaches from Samsung and Toshiba (and anyone else who has a similar approach).
One of the most fundamental attributes of any NAND Flash approach is the string current. This is the amount of current expected out of the string when reading a cell in the string. Its importance lies in the fact that it defines how long it takes to read whether a cell is storing a zero or a one. If the current is too small, it may not be discernible above the background current noise of the chip or may take a very long time to sense.
My 9-year old daughter is studying elementary electrical circuits at school here in Silicon Valley. Her homework is full of parallel and series circuits. One puzzle included a picture of many light bulbs connected in series to a battery. Then she had to double the number of bulbs in series and guess what would happen to their brightness. Needless to say, she had no interest in my analogy to vertical 3D NAND but, undaunted, let me use it here below.
To understand the relevance, have a look at figure 1 showing 16 3D NAND cells distributed over 4 vertical layers and 4 vertical channels. As in my last blog post, the channels are vertical green cylinders and the gates are horizontal red bars. The dark cylindrical sheath around each channel is a combination stack of thin dielectrics that allow electrical charge to be stored and is the origin of “Charge Trap Flash” (CTF). For those interested in history, the CTF approach has actually been around since 1968.
For the “Big 5” (Samsung, Toshiba, Hynix, Micron and SanDisk have all been talking about such 3-D NAND approaches) to double the memory capacity on a single chip using vertical channel 3D NAND, they will have to double the number of cells in the vertical direction.
Figure 2 shows the result. Notice how each channel doubles in length. Now you get the analogy with those series light bulbs, namely a longer series string means less string current and “dimmer light bulbs”.
Now, lengthening the string in NAND Flash is nothing new. In fact, the first string that Toshiba came out with in 1988 had 8 cells with each having a 1µm gate length. The most advanced 2D NAND’s now have 128 cells in a string. However, this path to longer strings has taken 25 years to complete. The reason is that it has been a second order parameter affecting die size compared to the usual lateral shrinks. Also, every doubling of string length cuts that string current in half ,all else being equal. In other words, those light bulbs are getting dimmer each time.
So if the NAND manufacturers have been able to increase string lengths over twenty-five years, what’s the big deal now with vertical channel 3D NAND? Well, it turns out that there are two crucial differences.
First, lengthening the string is the primary way they can increase single chip NAND memory capacities. In fact, it may be the only way. The reason is that lateral shrinking is exhausted. In other words, those vertical structures cannot be jostled and encouraged to stand closer together. This can be seen in figure 3 where two columns are shown.
Notice how a line from the center of one channel to the center of another channel includes twice the radius of one channel, twice the thickness of the CTF combo dielectric stack, twice the gate conductor extent, and the spacing between the gate conductors. That’s quite a lot of stuff, none of which can really shrink any further due to etch-and-fill reasons, impact to nonvolatile retention, and gate conductivity.
This means that Samsung’s V-NAND, initially at 24 layers, will need to go to 48 layers to double their 3-D NAND chip capacity.
Second, the starting point for string current is already quite low compared to the 2-D case and therefore any lengthening of the string will decrease it further from this low level.
To see why this is, I’ve stripped away all the layers to show the vertical channels by themselves in figure 4. The 3D drawing software is great at showing the disordered nature of this channel material. That’s the key. 2D NAND has electrical conduction taking place in a crystalline channel (the silicon wafer itself) while these vertical channel 3D approaches have conduction in a polycrystalline silicon channel.
Why should this matter? Well, imagine you are an electron that needs to get from one end of the NAND string to the other through the length of the channel. A particularly apt analogy is an ice skater. Anyone who has learned to skate looks forward to the perfectly smooth ice straight after the Zamboni ice resurfacer has done its job. Stepping out onto this ice, you are the electron in the 2D NAND crystalline channel, namely fast and well controlled (if you’ve had the right training obviously!).
Now imagine strapping on those skates and stepping out onto the surface of a glacier. Now you’re the electron making your way through the polycrystalline silicon 3D NAND channel. Imagine how slow you would be! No amount of training would help here! The glacier’s rough ice and ravines are analogous to the polycrystalline silicon’s grain boundaries and defects within the grains.
It turns out that the physics of this type of electrical conduction has been studied for many decades with a Nobel Prize awarded in 1977. The main thing to realize is that the disordered channel severely reduces your (the electron’s) mobility, which results in much lower currents than in crystalline channels.
If you want to learn more about the physics of this fascinating area, my group (at the time) and I published a study in the IEEE in 2004 several years too late for that Nobel Prize! (If you want a full copy, let me know at firstname.lastname@example.org). Don’t tell anyone, but it was this stuff that attracted me to the physics of semiconductor devices almost 30 years ago.
Now you can see that to double the vertical channel 3D NAND memory capacity will need a doubling of the channel length which is like doubling the glacier width that you (the electron) has to cross. The string current, already low, diminishes even further.
The importance of the string current is such that the manufacturers do not give its actual measured value in their technical academic publications but rather use the term “A.U.” for “Arbitrary Units”. Its strategic nature overrides any scientific qualms that may arise in the use of A.U.
Since I am not bound by such limitations, I can share some real experimental data on what levels of string current should be expected from these vertical channel 3D NAND approaches. But maybe that’s enough for this post and that juicy data can wait until the next one! ~ AJW