Samsung

IFTLE 403: TSMC 4th Generation CoWoS; 2018 Singapore EPTC Part 1

IFTLE 403: TSMC 4th Generation CoWoS; 2018 Singapore EPTC Part 1

Heterogeneous Integration spurs demand for 3D backend solutions Julian Ho reported in the Jan 10th issue of Digitimes that heterogeneous integration of diverse semiconductor components to support 5G, AI, automotive electronics, and IoT applications is gaining significant momentum, driving demand for system-in-package (SiP) and system-on-3D package (So3D) processes and boosting the importance of c... »

IFTLE 401: FOWLP for RF; D2W Hybrid Bonding; FOPLP in Samsung Watch

IFTLE 401: FOWLP for RF; D2W Hybrid Bonding; FOPLP in Samsung Watch

As its name implies, the International Wafer Level Packaging Conference (IWLPC) initially covered wafer-level packaging (WLP) technologies. As all conferences do, it soon expanded its scope to cover basically all advanced packaging topics including WLP, fan-out wafer-level packaging (FOWLP), 2.5D/3D, and advanced manufacturing and test, etc. Statistics from this year’s show include: 809 Atte... »

IFTLE 398: Samsung’s 256Gb 3DS (TSV-Stacked) RDIMM; IMAPS 2018 in Pasadena

IFTLE 398: Samsung’s 256Gb 3DS (TSV-Stacked) RDIMM; IMAPS 2018 in Pasadena

Samsung at the Leading Edge At the recent Samsung Tech Day, the company unveiled several new technologies: Their 7nm extreme ultraviolet (EUV) process node from Samsung’s foundry business SmartSSD – a field programmable gate array (FPGA) SSD, that will offer accelerated data processing and the ability to bypass server CPU limits QLC-SSD for enterprise and data centers that offer 33%t more... »

Citius, Altius, Fortius Redux: More From SEMICON Korea 2018

Citius, Altius, Fortius Redux: More From SEMICON Korea 2018

The Winter Games are over and the athletes returned home, and the SEMICON Korea 2018 teams from February have their sights on SEMICON China this month after all that snow-in-Seoul settled, but I still have a few more comments about the Electropackage System and Interconnect Product technical session SEMI organized for the afternoon of 01 February 2018, and on which I reported in my first installme... »

Citius, Altius, Fortius: Packaging Topics at SEMICON Korea 2018

Citius, Altius, Fortius: Packaging Topics at SEMICON Korea 2018

Winter 2018, and Korea is at the center of the world in both sports and in electronics. Sports, of course, because of PyeongChang, host city for the 23rd Olympic Winter Games, with participants ranging from Eritrea to Tonga, along with the usual cold-weather-country (Norway, Canada, Sweden, etc.) players who showed up for the Games. And electronics, of course, specifically semiconductor device fab... »

Mission Impossible? Not for SEMI!

Mission Impossible? Not for SEMI!

San Francisco’s Moscone Center (above), the traditional home of SEMICON West trade shows, is undergoing major reconstruction work. Looking at this picture of the South Hall you may ask yourself: “Can anybody organize a large trade show here and make it a big success?” My answer is: “YES, the SEMI team can! They did exactly this in July for SEMICON West 2017!” With some very creative spac... »

A Fan-Out Wafer Level Packaging Epiphany

A Fan-Out Wafer Level Packaging Epiphany

I’ve had an epiphany regarding fan-out wafer level packaging (FOWLP). Epiphany: “A usually sudden manifestation or perception of the essential nature or meaning of something.” In FvT’s piece “Spotlight on FOWLP, Monolithic 3D IC, and 3D TSVs,” (13 May 2015) I am quoted saying: “Show me where monolithic or FOWLP is … can’t seem to find it.” I wasn’t alone in my thinking; we re... »

2015 Retrospective and Outlook for 2016: 3D NAND Flash One-upmanship

2015 Retrospective and Outlook for 2016: 3D NAND Flash One-upmanship

“On average since 1885, the yearly height record has gone up by 10 feet (3 meters) each time. Since the 1960s the pace has picked up to 16 feet.” This is not 3D NAND Flash but skyscraper heights in a recent article in The Economist (the power of visual data presentation!). Similarly, 3D NAND height, as in the number of device layers, has become a metric for one-upmanship between the Flash man... »

Can 3D Super-NAND Improve Cost-per-Bit for 3D NAND?

Can 3D Super-NAND Improve Cost-per-Bit for 3D NAND?

The 3D NAND floodgates just opened a little wider with today’s announcement from BeSang that it has developed 3D Super-NAND technology, based on a monolithic 3D IC process, True 3D™ IC, claiming to be the “lowest cost-per-bit in the NAND market.” With all the recent 3D NAND discussion and announcements about Samsung, Toshiba, and Intel and Micron’s 3D X-point, I wanted to know more. Spec... »

With 3D Memory Cubes You Can Finally Break Down the Dreaded Memory Wall

With 3D Memory Cubes You Can Finally Break Down the Dreaded Memory Wall

In July and August schools are closed and many people like to take vacation. Typically nothing major happens during these months. Not this year! It was a lively August, if you consider the recent “adjustments” in the stock markets worldwide as a series of events disrupting the summer doldrums. But I am not here to give you investment advice. So let’s move on to a subject I am more familiar w... »

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