The Winter Games are over and the athletes returned home, and the SEMICON Korea 2018 teams from February have their sights on SEMICON China this month after all that snow-in-Seoul settled, but I still have a few more comments about the Electropackage System and Interconnect Product technical session SEMI organized for the afternoon of 01 February 2018, and on which I reported in my first installment on the topic.

I will say, again, that I was in excellent company! Amkor, SK Hynix, KAIST, nepes, Samsung, ASE, STATS ChipPAC (now known as JCET), GLOBALFOUNDRIES, NVIDIA, and Yole Developpement all spoke at the session, as did I, to a room filled with attendees.

Thank you, SEMI, for organizing one very interesting afternoon.

I covered the talks from STATS ChipPAC, SK Hynix, Amkor, NVIDIA, KAIST, and Samsung Electronics in my earlier piece; now, let’s get down to business on the four remaining ones.

You no doubt have been hearing about 5G just about everywhere these days, even if you have yet to experience it yourself; “official” rollout will be at the 2020 Olympic Summer Games, in Tokyo, but I’m expecting we all might get a taste before then. GLOBALFOUNDRIES is on the 5G case, as we heard from Christian Goetze in his talk on 60GHz antenna array packaging using silicon-to-package co-design. The goal? To produce a “reliable, highly integrated, mmWave and low loss optimized package design which supports mixed signal SoCs and an integrated antenna for a reasonable price.”

5G: it’s not your father’s phone call. Rather, 5G is a combination of technologies resulting in energy efficient, high speed/low latency communications between a massive number of devices for (potentially) mission critical applications. Think connected cars and autonomous driving.

And what we need for that, including the cooperation of our present material sets and standard circuit elements with 60GHz frequency operation, is an ADK – an Assembly Design Kit, so that present and future users of foundry services for 5G applications can take advantage of the cost optimization that will result from the standardization of these for-5G flows and processes.

Oscar Shih, ASE, spoke on 2.5DIC Technology and Solutions, reminding us about the overall importance of yield, whether die yield at the fab, or interposer and assembly yield at the OSAT. ASE is shipping good volumes of real products using 2.5DIC technology, citing a variety of package sizes, some quite large.

I don’t have copies of the presentation slides from Jeongsoo Byun, Samsung Electro-mechanics, but from my notes I recall with surprise his use of ® in the term FOPLP®. What’s up with that? Anyway, for fan-out panel level packaging, Samsung Electro-mechanics is doing a chip-first process, embedding die and other components in cavities created in PCB-like substrates. Yield for the process is said to be 99%, and there is a pretty aggressive roadmap for taking RDL features from 5µm lines and spaces all the way down to 1.7µm L/S in 2019, at which point in time there will also be a chip-last process flow available.

There’s always been talk that a practical approach to implementing fan-out panel level packaging would be to piggyback on the work already done on earlier generations of LCD panels, using LCD tools built for Gen 3.5, or maybe Gen 4, displays. Well, folks, nepes is doing just that, as Tae-Hoon Kim informed us in his “Panel Level Packaging New Era Advanced Packaging Solution” talk. FOPLP at nepes is being done on 600mm x 600mm panels, since 2016, and it looks like these very large panels (vPLP™) also allow for a process flow where multiple wafers are processed together at a time. Applications include automotive radar and fingerprint sensors.

And there you have it, just in time for me to be at IMAPS DPC 2018 for my talk there on 07 March. My topic is “Linear Transport Degas, Pre-Clean, and PVD Processes for RDL Barrier/Seed Formation in Fan-Out Packaging,” which I will be happy to share with you once I go live. And my SEMICON Korea 2018 presentation, on “Ion Beam Source for RDL Pre-Clean in Fan-Out Wafer and Fan-Out Panel Level Packaging,” is also available to you directly, should you please just ask.

From Santa Clara, CA, thanks for reading. ~PFW

Paul Werbaneth

Paul Werbaneth is a long-time Contributing Editor at 3D InCites. Since entering the semiconductor industry…

View Paul's posts

Become a Member

Media Kit