STATS ChipPAC

MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained

MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained

Multichip module (MCM),  system-in-package (SiP), system-on-chip (SoC), and heterogeneous integration are all important semiconductor packaging technologies. They deserve to have, at the very least, a book written about them. However, herein I would like to give these technologies very simple descriptions. if you don’t mind. MCM MCM integrates different chips and discrete components side-by-si... »

Executive Viewpoint: The New Advanced Packaging Landscape

Executive Viewpoint: The New Advanced Packaging Landscape

You might recall that a few year’s back (October 2013, to be precise), 3D InCites’ regular blogger, Paul Werbaneth, had the opportunity to interview Dongkai Shangguan, then CEO of the National Center for Advanced Packaging (NCAP) in Wuxi, China, which he helped found along with nine investors. They talked about lots of timely topics: the importance of industry-wide collaboration to bring down ... »

Ideas for Co-optimizing Chip-Package Design

Ideas for Co-optimizing Chip-Package Design

In a recent blog sharing my impressions of July’s Semicon West, I complained a bit about the lack of substantial IC packaging topics at this large IC manufacturing conference and also mentioned that I had observed the same problem at June’s Design Automation Conference. I am glad that I was fairly diplomatic with my complaint, because the day after Francoise posted my blog, SEMI, our industry... »

TSV MEOL Process Flow for Mobile 3D IC Stacking

TSV MEOL Process Flow for Mobile 3D IC Stacking

Moore’s law is approaching physical limitations of CMOS scaling, and three dimensional (3D) integration technologies have been proposed as solutions. Wide band transmission between logic and memory is becoming indispensable for not only mobile products, but also other products related to network systems such as servers and data centers. These days, 3D integration with Through Silicon Vias (T... »

SEMICON Singapore 2014: A Rosy Outlook for 2.5D and 3D ICs

SEMICON Singapore 2014: A Rosy Outlook for 2.5D and 3D ICs

This week, at the invitation of SEMI Southeast Asia, I made the monumental trek from Phoenix, AZ to Singapore to attend SEMICON Singapore. While I know many of my industry colleagues make these journeys in the regular course of business, this was a new experience for me and my first visit to both Singapore and SEMICON Singapore, which has historically been focused on the packaging, test and assemb... »

Semi Trade Pubs Talk 3D, Just in time for SEMICON West

Semi Trade Pubs Talk 3D, Just in time for SEMICON West

That Jan Vardaman, she’s so clever! I just finished reading her column on ECTC 2013 in Printed Circuit Design and Fab, and thought her quippy, Las Vegas-y references in the opening paragraph were right on the money. Vardaman’s take on ECTC was similar to my own, discussed here in my review of the foundry panel session.  She also offers some great take-aways from some of the sessions that I m... »

A*STAR IME, STATS ChipPAC and Qualcomm collaborate to develop low cost interposer technology

A*STAR IME, STATS ChipPAC and Qualcomm collaborate to develop low cost interposer technology

Singapore 29 May, 2013– Singapore’s A*STAR Institute of Microelectronics (IME), Qualcomm Technologies Inc., a wholly owned subsidiary of Qualcomm Incorporated, and STATS ChipPAC have announced a collaboration to develop technology building blocks for Low Cost Interposers (LCI) for 2.5D ICs. “2.5D/3D IC technology provides ample opportunities to further increase functionality and perf... »

3D ICs News in Brief – Jan. 19-29

3D ICs News in Brief – Jan. 19-29

While there is still a lot to report about the European TSV Summit, I wanted to catch everyone up on some recent developments at companies that have come my way via press release; beginning with the most recent: STATS ChipPAC and UMC announced that they have demonstrated the world’s first TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration. The companies re... »

3D TSV Summiit

European 3D TSV Summit: 3D TSVs Come of Age

Here I am, on my way back from Minatec Campus in Grenoble, France, where I attended SEMI Europe’s premiere European 3D TSV Summit. It was such a whirlwind few days, jam-packed with quality presentations demonstrating recent progress in all things TSV by the semiconductor manufacturing community and fabulous meals with industry colleagues and friends that this flight home is the first time I’ve... »

STATS ChipPAC Advances TSV Capabilities; Qualifies 300mm MEOL and Low Volume Manufacturing

Outsourced Semiconductor Assembly and Test (OSAT) provider, STATS ChipPAC Ltd., has announced qualification of its 300mm middle-end-of-line (MEOL) manufacturing operation for Through Silicon Via (TSV) capabilities, and will transition to low volume manufacturing.  STATS ChipPAC says it is firmly engaged with multiple strategic customers on TSV development programs that support the semiconductor »

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