Semi Trade Pubs Talk 3D, Just in time for SEMICON West

Semi Trade Pubs Talk 3D, Just in time for SEMICON West

That Jan Vardaman, she’s so clever! I just finished reading her column on ECTC 2013 in Printed Circuit Design and Fab, and thought her quippy, Las Vegas-y references in the opening paragraph were right on the money.

Vardaman’s take on ECTC was similar to my own, discussed here in my review of the foundry panel session.  She also offers some great take-aways from some of the sessions that I missed; in particular the evening panel that focused on packaging challenges across the wireless market supply chain, which addressed monolithic silicon integration versus 3D IC, or what Nokia called “super chips.”  You can find her article, titled Playing the Collective Hand, here.

In the latest issue of Solid State Technology, EV Group’s Paul Lindner and Thorsten Matthias discuss paradigm changes in 3D-IC manufacturing.  This article offers a thorough back-story on the evolution of TSVs and 3D ICs; and how the process flows have changed from the initial introduction of these technologies in CMOS image sensors and other high-end applications that are not quite as cost-sensitive as consumer applications, such as FPGAs.  Lindner and Matthias conclude that “3D integration can provide many benefits, but only where it can prove to be a ‘sustainable innovation’ and not just a ‘disruptive innovation.’”  In supporting this idea, they cite “The Innovator’s Dilemma” by Harvard Professor Clayton Christensen, explaining that, “ innovations cannot be introduced in value networks where they are considered “disruptive” no matter how technically mature, cheap or well established for other applications they are. However, in a different value network where the innovation is sustainable, the users can hone their skills and build expertise.”  This is the hope for 3D IC moving from high-end applications to consumer applications.

Chip Scale Review’s SEMICON West Issue takes on a number of hot 2.5D and 3D related topics, including an editorial by yours truly on one of my latest quests, the introduction of the term “Interconnectology” to the semiconductor manufacturing value chain lexicon.

Also featured in this issue is a comparison of organic, glass and silicon interposer options for 2.5D and 3D technologies, contributed by Georgia Tech’s Rao Tummala. In it, he outlines the benefits and limitations of each material, and hones in on a comparison of lithographic ground rules, bump I/O pitch and relative cost.  A long-time champion of glass, Tummala concludes that “glass is poised to fill the gap between submicron wafer–based Si lithography and 10µm panel-based organic packages.”

And lastly,  a team from STATS ChipPAC contributed  a feature on advanced wafer-level packaging technologies for 3D Integration that focuses on the company’s offerings in fan-out wafer level packageing (FO-WLP), TSV technologies, and 3D FO-WLP. Authors Seung Wook Yoon, Patrick Tang, Steve Anderson, and Raj Pendse, talk about the 2.5D and 3D evolution, the need for a collaborative ecosystem to hammer out co-design and standards. Variation in packaging technologies offer choices to meet the needs of differentiated device requirements. This article offers a high-level overview of STATS’ offerings in the 2.5D and 3D space.