Ideas for Co-optimizing Chip-Package Design

Ideas for Co-optimizing Chip-Package Design

In a recent blog sharing my impressions of July’s Semicon West, I complained a bit about the lack of substantial IC packaging topics at this large IC manufacturing conference and also mentioned that I had observed the same problem at June’s Design Automation Conference. I am glad that I was fairly diplomatic with my complaint, because the day after Francoise posted my blog, SEMI, our industry’s manufacturers’ organization and MEPTEC, an organization focused on IC Packaging and Test, announced a joint conference, with the very fitting title “The Great Miniaturization: Systems and Packaging.” I am really glad to see that these powerful organizations jointly address IC packaging and emphasize how significant the contributions of IC packaging technology are for the success of today’s electronic systems.

For their joint conference on November 10 and 11 at the Biltmore Hotel in San Jose, these two organizations are recruiting wafer manufacturing and IC packaging and test experts to present why and how IC packaging significantly contributes to meeting our customer’s demands for smarter, smaller, lower power and of course lower cost electronic systems. I look forward to reporting about this very import event, not only because co-optimizing dies and package can add significant value to 2.5D and 3D ICs, but also because the success of many single die designs depends heavily on performance and cost of its package.

In my years at VLSI Technology I learned the hard way – on a high-visibility mobile device project and shortly thereafter on a super computer program – how important the right packages can be for the success of the dies they encapsulate. I do not recommend making the same, very painful mistakes. That’s why I am glad to see that EDA firms, IC vendors, and assembly houses are working together to enable chip-package co-optimization. One such successful cooperation involving Mentor Graphics, Qualcomm and STATS ChipPAC, was recently described here.

This pilot project identified a number of essential elements of Assembly Design Kits (ADKs) and how to utilize the data provided by ADKs. Just like PDKs have, for many years already, conveyed to IC designers successfully what the wafer fab partner is capable of providing with reasonable yields; ADKs can streamline the development cooperation between assembly houses (also called OSATs) and IC designers. ADKs can also reduce time to market, lower risk, increase yields and, most importantly, can lower cost of the packaged product as well as enable higher profit margin to share between the parties contributing.

My work in various areas of the 2.5/3D-IC Ecosystem is giving me plenty of opportunity to observe the interaction between EDA vendors, large assembly houses and their customers, both IDMs and fabless IC vendors. Allow me to first share some of my observations:

  • Our industry’s EDA tools developers and IC designers have mostly Electrical Engineering degrees, while many IC packaging experts have Mechanical or Chemical degrees. While all parties are very competent in their individual fields, the “common ground between them” appears to be limited and often complicates cooperation.
  • Large IC vendors employ their own IC packaging experts, as in-house development partners for their IC designers, and as bridge to the chosen assembly partner(s).
  • Today many applications require custom packaging solutions to meet stringent form-factors, performance, and cost requirements. Today assembly houses develop a range of, what I would call core capabilities, and the IC designers, together with their in-house IC packaging experts, utilize these core capabilities as starting points for their particular custom packaging solution. A structured way of describing these core capabilities – in an ADK – appears to be welcomed by all parties involved. They expect ADKs to minimize iterations, time to market, stress, and communication problems, as well as packaged unit cost.
  • Beyond the complex cooperation between IC vendors and assembly houses, EDA support is also essential. The above referenced pilot project already shows an EDA vendor demonstrating part of a chip-package co-optimization flow. A complete co-optimization design flow takes the data from the wafer foundry’s PDK and the assembly partner’s ADK and allows the customer’s design team, comprising IC- and package experts, to evaluate available chip-package combinations, analyze how modifications on either or both the chip and the package impact the resulting product, choose a compelling combination and accurately verify if it meets all necessary requirements. The above-referenced pilot project describes some of these steps in greater depth.
  • Just like PDKs from wafer fabs have a number of commonalities, but also essential differentiators, the assembly houses too want to include differentiating capabilities in their ADKs. Also, like wafer fabs, assembly houses model their core capabilities differently and want to provide only encrypted, machine readable data as inputs for the chip-package co-design flows, the EDA partner develops with them.
  • I also learned that the large assembly houses already have partial ADK solutions in place today, to covey some of their capabilities to customers in a structured way. They, and their customers, are interested to improve accuracy and timeliness of the data flow between them and want EDA vendors engaged to develop more complete, easy-to-use, and quick-to-update ADKs. Together with the PDKs, ADKs can feed all necessary data for a die-package co-optimization flow into the user’s design environment. However, like for every important project, the needed development efforts still have to be justified and the necessary payback needs to be demonstrated.
  • The interest in interposer-based designs and low-cost Fan In and Fan Out Wafer-level-packaging (FI- and FO-WLP) as well as panel-level packaging is rapidly increasing for single die and especially multi-die ICs, as design complexity and cost for continued feature-size shrinking is increasing exponentially. All three camps appear to be motivated to work together to enhance the existing, partial ADKs; streamline the current modeling methods for all IC package components; establish release/updating procedures; deploy encryption; and plan to utilize ADKs to cut development time, risk, and cost as well as reduce packaged unit cost.

After highlighting ADK benefits, let’s have a closer look at an Assembly Design Kit and discuss what to include and exclude:

  • Data about cost: NO. While some designers are asking to include cost-data in the ADKs to allow for cost-trade-offs, I recommend not to do so. Cost, and with it price, is very volume dependent, customer specific, and changes frequently over the time of a development program. Purchasing departments should recommend to their IC and packaging experts what to consider and why.
  • Availability information and lead-times: YES. By specifying package characteristics of readily available packages up-front and in great technical depth, assembly houses may be able to steer customers’ demand towards existing packages and minimize tooling cost and development time required for custom solutions.
  • Thermal characteristics of the package components: YES. One of the major design challenges is to find a die(s)-package combination that avoids over-heating of the die(s) and temperature-related failures and/or eventual reliability problems. Specifying one “°C per Watt” number is no longer sufficient. Considering hot-spots on a single die, or a combination of hot-spots on multi-die designs, demands more accurate information about the thermal resistance of multiple paths that can contribute to cooling specific areas of the die(s). Also, a link to consider the cooling impact of the board and/or a heat sink needs to be provided.
  • Thermal-mechanical interactions: YES, YES, YES: As I mentioned above, I learned the hard way that different thermal coefficients of expansion (CTE) can destroy a die, especially when thinned to ~100µm or even < 50µm. Silicon’s CTE is significantly lower than the materials used for underfill and package substrate. Also, copper TSVs, interconnect wires, copper-studs, micro-balls and other package components can exert significant mechanical strain and even destroy a die during assembly or operation, if not carefully considered. See CTE details here.
  • This important point brings us to accurate Modeling: YES. Modeling of overall package characteristics and individual package components is challenging, but essential. While assembly houses work very hard to capture all these data, they depend on their material suppliers to provide numbers, not just for typical characteristics, but with best and worst case ranges. Considering that material suppliers typically only sell a small portion of their production to the “picky semiconductor industry”, this corner of our supply chain needs some extra attention.

Let’s not get too detailed in this blog, but discuss only one more topic here: The data exchange between assembly houses and their customers. While the customers demand accurate (typical/best/worst-case numbers) and up-to-date information, the assembly houses, facing very thin margins, have to run a very lean operation and need a very efficient way to generate these numbers in a timely fashion and need a mechanism to protect them. Just like I experienced in the early days of PDKs, EDA vendors should again work with the supply chain partners, to develop accurate and efficient modeling techniques and a powerful data exchange format – e.g. XML models appear to be preferred widely. Last, but not least, the data needs to be encrypted, so that only the design tools of the EDA partner(s) can utilize this info to simulate and co-optimize the die(s)-package interactions.

Let’s circle back one more time to the recent blog describing the Mentor Graphics – Qualcomm – STATS ChipPAC cooperation. The described pilot project gives you much more technical details, and several examples for design steps, than this blog was intended to cover. Looking forward to your cooperation on the way to accurate, up-to-date and IP-protecting Assembly Design Kits, to complement the widely used Process Design Kits, and jointly enable user-friendly die(s)-package co-optimization. ~ Herb