Mentor Graphics

Solving the Design and Verification Challenges of High Density Advanced Packaging

Solving the Design and Verification Challenges of High Density Advanced Packaging

Today’s electronic products present new challenges to product development teams. As a result, there is a constant push to improve product quality and design efficiency through the use of new design technologies. For example, system-scaling demands change as Moore’s law becomes increasingly difficult to maintain, thus driving growth of innovative PCB and packaging technologies such as: High-den... »

Announcing the Winners of the 2017 3D InCites Awards!

Announcing the Winners of the 2017 3D InCites Awards!

The 2017 3D InCites Awards program has turned out to be the most exciting yet! We had as many as seven nominees in some fields (supplier of the year), and tallied just over 17,529 votes in total! We also saw a considerable increase in nominees using social media to promote their participation in this year’s event. As heterogeneous integration, fueled by advanced packaging and 3D integration, mov... »

DAC 54: From Grey to Colorful and Solutions-minded Messaging

DAC 54: From Grey to Colorful and Solutions-minded Messaging

The 54th Design Automation Conference (DAC 54) at the Austin Convention Center was very different, compared to the last several years’ events. Walking the exhibition floor, listening to keynotes, SKY talks and CEO interviews I got the following key impressions: While still representing a big part of the audience, the grey-haired men (like myself) were less dominant this year. Many younger people... »

Executive Viewpoint: Breaking The Chicken and Egg Cycle for HDAP

Executive Viewpoint: Breaking The Chicken and Egg Cycle for HDAP

  For several years now, Herb Reiter, eda2asic, and John Ferguson, Mentor Graphics, have been evangelizing about the necessity of assembly design kits (ADK), similar to the process design kits (PDKs) for chip designers, to help drive ecosystem capabilities for what is collectively now being called high density advanced packaging (HDAP), comprising 2.5D IC, 3D IC and high density fan-out wafer... »

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3D IC Test: Now and The Road Ahead

Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I presented a tutorial titled “What is New in 3D, Digital Testing?” and I’ll summarize the main points here. I consider test standards and test challenges, which include known-good-die and testing stacked die. The two main goals of 3D IC test are to improve the pre-packaged test quality and to ... »

DesignCon 2016: Where the Chip meets the Board and Great Ideas Come to Life

DesignCon 2016: Where the Chip meets the Board and Great Ideas Come to Life

DesignCon 2016 at the Santa Clara Convention Center gave football fans among us an opportunity to watch the preparation work for Super Bowl 50. Right across the street from the Convention Center is Levi Stadium, where on Sunday, February 7, this year’s champion will be crowned. Impressive, but let’s not digress and focus on DesignCon. For me, in my role as business developer for innovative pro... »

Why Do We Need Assembly Design Kits for Packages?

Why Do We Need Assembly Design Kits for Packages?

In our last article, we talked about a project we participated in to test the feasibility of an assembly design kit (ADK) for package design verification. This time, we’d like to delve a little more into the reasons why assembly design kits are needed. Naturally, one of the reactions to our article was “But I already have requirements from my package house. Why do I need an ADK?” True, packa... »

Ideas for Co-optimizing Chip-Package Design

Ideas for Co-optimizing Chip-Package Design

In a recent blog sharing my impressions of July’s Semicon West, I complained a bit about the lack of substantial IC packaging topics at this large IC manufacturing conference and also mentioned that I had observed the same problem at June’s Design Automation Conference. I am glad that I was fairly diplomatic with my complaint, because the day after Francoise posted my blog, SEMI, our industry... »

Assembly Design Kits are the Future of Package Design Verification

Assembly Design Kits are the Future of Package Design Verification

Unlike the traditional system-on-chip (SoC) design process, which has fully qualified verification methods embodied in the form of process design kits (PDKs), chip design companies and assembly houses have no integrated circuit (IC) package co-design sign-off verification process to help ensure that an IC package will meet manufacturability and performance requirements. Package die are often produ... »

IRT Nanoelec Partners Achieve 3D Chip-stacking Technology and 3DNoC Framework for Digital Processing

IRT Nanoelec Partners Achieve 3D Chip-stacking Technology and 3DNoC Framework for Digital Processing

GRENOBLE, France – July 09, 2015 – IRT Nanoelec, an R&D consortium focused on Information and Communication Technologies (ICT) using micro- and nanoelectronics, and its partners CEA-Leti, STMicroelectronics and Mentor Graphics have realized an innovative 3D chip, called “3DNoC” to demonstrate the use of 3D stacking technology in scalable, complex digital systems-on-chip (SoCs).... »

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