Latest Posts
Optimizing Your SoCs and ASICs to Design PCBs More Cost Effectively
Many high-performance systems today use custom ASICs or SoCs to provide the necessary computational power and data bandwidth demanded by... Electromagnetic Modeling of Three-dimensional Integrated Circuits
Three-dimensional Integrated circuits (3DIC) are generating increased interest as a way to increase speed and density while reducing power and... Solving the Design and Verification Challenges of High Density Advanced Packaging
Today’s electronic products present new challenges to product development teams. As a result, there is a constant push to improve...
Announcing the Winners of the 2017 3D InCites Awards!
The 2017 3D InCites Awards program has turned out to be the most exciting yet! We had as many as...
DAC 54: From Grey to Colorful and Solutions-minded Messaging
The 54th Design Automation Conference (DAC 54) at the Austin Convention Center was very different, compared to the last several...
Executive Viewpoint: Breaking The Chicken and Egg Cycle for HDAP
For several years now, Herb Reiter, eda2asic, and John Ferguson, Mentor Graphics, have been evangelizing about the necessity of assembly...
3D IC Test: Now and The Road Ahead
Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I...
DesignCon 2016: Where the Chip meets the Board and Great Ideas Come to Life
DesignCon 2016 at the Santa Clara Convention Center gave football fans among us an opportunity to watch the preparation work...
Why Do We Need Assembly Design Kits for Packages?
In our last article, we talked about a project we participated in to test the feasibility of an assembly design...
Ideas for Co-optimizing Chip-Package Design
In a recent blog sharing my impressions of July’s Semicon West, I complained a bit about the lack of substantial IC...
Assembly Design Kits are the Future of Package Design Verification
Unlike the traditional system-on-chip (SoC) design process, which has fully qualified verification methods embodied in the form of process design...
IRT Nanoelec Partners Achieve 3D Chip-stacking Technology and 3DNoC Framework for Digital Processing
GRENOBLE, France – July 09, 2015 – IRT Nanoelec, an R&D consortium focused on Information and Communication Technologies (ICT) using...
Designing in 3D? Don’t Make These DFT Mistakes
The semiconductor industry hasn’t adopted 3D ICs as quickly as many in the industry expected. There are some barriers that...
Bumps are the Elephant in the Wafer Stress Room: NCCAVS Joint User Group Meeting On 3D Packaging
The Northern California Chapter of the America Vacuum Society has, for years, run a very strong program of ongoing User...3D EDA Tools – Coming out of the Woodwork
That didn’t take long. A post about one EDA tool introduction inspired a comment about a 3D layout editor that’s...EDA Approaches to 3D IC Tools
When I was in high school and then in college, I used my mother’s Smith-Corona MANUAL typewriter to write all...