Many high-performance systems today use custom ASICs or SoCs to provide the necessary computational power and data bandwidth demanded by their host system, whether it’s a network storage device, network data switch, complex industrial equipment controller, or a critical core module of a defense system. And they are not getting any smaller or slower as silicon process nodes shrink and memory demands continue to grow. The result can be a nightmare for the system PCB design team who have to integrate this often huge (size and number of PCB level connection balls) device while maintaining the overall integrity of the PCB-based system while ensuring signal layer count and overall PCB size stay within system and cost constraints.
This paper demonstrates the causal relationship between PCB Signal to ASIC/SoC pin assignment and the product’s profit margin. It also defines opportunities for generating significant competitive advantages without incurring significant time or cost penalties.
Mentor, a Siemens Business, developed Xpedition® Substrate Integrator in partnership with some of the world’s largest and most influential semiconductor and systems companies. The unique flow results in substantial costs savings for electronic component/device and system PCB developers and its lightweight, graphical, canvas based environment enables fast, multi-substrate, what-if rapid prototyping with concurrent interconnect optimization across SoC/ASIC, package, and PCBs.
Xpedition Substrate Integrator can radically increase design productivity and overall device performance while optimizing logical connectivity that can reduce PCB layer count, interconnects, and via usage. Its’ PCB-driven package-optimization process uses a current or reference PCB design to optimize critical signal performance and enable optimization of the PCB/package interfaces.
The combination of technology leadership and strong partner-customers supported the development and validation of PCB optimization, turning it into a key competitive advantage for system PCB design teams.