SoC

Optimizing Your SoCs and ASICs to Design PCBs More Cost Effectively

Optimizing Your SoCs and ASICs to Design PCBs More Cost Effectively

Many high-performance systems today use custom ASICs or SoCs to provide the necessary computational power and data bandwidth demanded by their host system, whether it’s a network storage device, network data switch, complex industrial equipment controller, or a critical core module of a defense system. And they are not getting any smaller or slower as silicon process nodes shrink and memory dema... »

The 14th 3D ASIP Conference Addresses a Spectrum  of 0pportunities, Part 1

The 14th 3D ASIP Conference Addresses a Spectrum of 0pportunities, Part 1

Several years before I started promoting 3D IC benefits in 2008, a small team of industry visionaries founded the 3D Architectures for Semiconductor Integration and Packaging conference (3D ASIP Conference). Rechristened to 3D Architectures for Heterogeneous Integration and Packaging (still 3D ASIP), each December sees several hundred key players from across the supply chain meeting to discuss mar... »

MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained

MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained

Multichip module (MCM),  system-in-package (SiP), system-on-chip (SoC), and heterogeneous integration are all important semiconductor packaging technologies. They deserve to have, at the very least, a book written about them. However, herein I would like to give these technologies very simple descriptions. if you don’t mind. MCM MCM integrates different chips and discrete components side-by-si... »

Outlook 2017:  SoC Goes on a Dielet

Outlook 2017: SoC Goes on a Dielet

It’s 2017, and system-on-a-chip (SoC) is headed for a dielet. At least that’s my 2017 outlook, based on takeaways from some of the recent conferences I’ve attended, including, to close out 2016, 3D ASIP last month in Burlingame, CA. SoC has been packing on weight in recent years, and it’s beginning to show, to SoC’s detriment. For example, the old ISO defect density rules from my early I... »

An Open Letter to Chip and System-level Designers Regarding 3D Integration

An Open Letter to Chip and System-level Designers Regarding 3D Integration

Dear Chip and System-level Designers, Allow me to introduce myself. My name is Françoise von Trapp, and I am known in the semiconductor industry as “The Queen of 3D”. This is because I have held a deep interest in 3D integration technologies, and have devoted the past 7+ years to following the development of the processes involved from proof of concept through to manufacturability, and report... »

GSA Silicon Summit: What’s next for the 2.5D/3D Ecosystem?

GSA Silicon Summit: What’s next for the 2.5D/3D Ecosystem?

Due to schedule conflicts, I was unable to attend this year’s Silicon Summit, which took place April 10, 2014 at the Computer History Museum, and featured a segment titled GSA Silicon Summit 2014: 2.5D/3D Ecosystem – What’s Next? Luckily, Rick McClellen, director of business development at Ziptronix briefed me on the event key takaways, which I’ve noted here and offered some of my own obse... »

3D Integration Workshop Faces Reliability Challenges Head On

3D Integration Workshop Faces Reliability Challenges Head On

The Friday 3D Integration Workshop at DATE 2014 once again found me among friends, as an intimate group of about 30 gathered to spend a day sharing knowledge gained since last year’s workshop. My key take-away for the day was how to achieve reliability and robustness. Jürgen Wolf, director of the Fraunhofer IZM-ASSID 3D integration program stepped in as keynote speaker to replace Yole Développ... »

Successful 2.5D Test Vehicle Project Launched by GLOBALFOUNDRIES, Open-Silicon and Amkor Technology

Successful 2.5D Test Vehicle Project Launched by GLOBALFOUNDRIES, Open-Silicon and Amkor Technology

GLOBALFOUNDRIES has unveiled details of a 2.5D test vehicle project that demonstrates the value of its open and collaborative approach to delivering next-generation chip packaging technologies. The company, in partnership with Open-Silicon (chief architect) and Amkor Technology, Inc. (assembly and test), jointly exhibited a functional system-on-chip (SoC) solution featuring two 28nm logic chips, w... »

ASMC 2013 and 3D IC: Time to Volume, Time to Via

ASMC 2013 and 3D IC: Time to Volume, Time to Via

What is today’s biggest threat to continued growth in the semiconductor industry? Subramani Kengeri, Vice President, Advanced Technology Architecture, GLOBALFOUNDRIES, opening the 24th annual SEMI Advanced Semiconductor Manufacturing Conference in Saratoga Springs, NY, asked just that question in his keynote address. (Asked it twice, actually; once at the beginning of his provocative talk, and o... »