An Open Letter to Chip and System-level Designers Regarding 3D Integration

An Open Letter to Chip and System-level Designers Regarding 3D Integration

Dear Chip and System-level Designers,

Allow me to introduce myself. My name is Françoise von Trapp, and I am known in the semiconductor industry as “The Queen of 3D”. This is because I have held a deep interest in 3D integration technologies, and have devoted the past 7+ years to following the development of the processes involved from proof of concept through to manufacturability, and reporting on this progress here on 3D InCites. (If this is your first visit to the site, I encourage you to have a look around.)

It has come to my attention that while many of you are seeking new ways to deal with the increasing complexity of SoC designs, you may not have thought about 3D integration as a possible solution. Consider this: breaking up an SOC design into specific functions such as graphics node, cache node, CPU node, analog node, allows you to manufacture each technology in its optimal node instead of doing everything in the same node, based on the most complex node required by a particular function. 3D IC processes enable the stacking of these disparate technology nodes either in 2.5D configurations on an interposer, or in a 3D IC stack. It also allows you to achieve the performance benefits you hope to gain from further scaling, but at a much lower cost. Does that sound like a solution to you?

You may or may not have been following the course of 3D integration technologies through its developmental years. You may have heard or read about it at one time or another and considered it as a solution, but didn’t look further because it wasn’t available in manufacturing to solve your immediate problems. You might have even heard a really interesting keynote at an industry event, and thought it sounded promising but somehow it dropped off your radar as the next project came to you and you reverted to traditional methods to solve the next design challenge.

It is my pleasure to inform you that the waiting time is over, and 3D ICs are ready to implement.

Throughout all the time I have been writing about 3D integration, the target applications have not changed (high-end data centers, medical devices, consumer mobile products); and the market drivers have not changed (improved performance, lower power consumption, smaller footprint); yet the roadmap for adoption has been pushed out each year, and the finger of blame has been pointed in many directions.

In the beginning, it was the seemingly insurmountable technology challenges that were the cause. But one by one, through large investments of R&D dollars and Euros, and through collaboration between research centers, suppliers, and manufacturers, these challenges have been addressed.

Next, the hold up was a lack of design tools, thermal challenges, and test solutions. But the design tools are now available. Design for test methodologies are coming along, and probe and test tooling is also available. While the kinks are still being worked out in these areas, manufacturers have assured us that these issues (including thermal) are no longer a showstopper.

Supply chain issues have been solved through open platform and collaborative approaches. Ultimately, the customer will decide who they want to manufacture their products. But everybody – the foundries, the OSATS, and the IDMs – claim they are ready to roll once someone pulls the trigger.

By far the worst culprit for the continued adoption delay has been cost. But in reality, “too costly” is a matter of perspective. Yes, 3D IC stacking using through silicon via (TSV) technology may cost more than traditional wire bonds; but that is no longer an apples-to-apples comparison, because the performance benefits that can be realized with 3D ICs are not possible to achieve with wire bond. 3D ICs carry a tremendous value-add that customers must be willing to pay more for. And when compared with CMOS scaling for 2D SoC designs, the cost of 3D SoCs has been shown to be considerably less. Furthermore, it is believed that once 3D ICs are manufactured in volume, costs will come down as processes are optimized to reduce cost of ownership (CoO).

Year after year, conference after conference, those involved in developing all these 3D IC solutions come together to present their latest accomplishments, and to bolster each other up and cheer each other on, and even try to show each other up that our product, or tool, or material is better than the last guy who presented. We have panels that discuss the remaining challenges, and the supply chain, and speculate when and who is going to take the lead on this. And we wonder why, when 3D is such a great innovation, it hasn’t taken off yet?

And then it hit me. All these years, we’ve been preaching to the choir! We don’t need to convince each other that 3D ICs are the path to the future of the semiconductor industry. We have been believers, champions, and ambassadors all along. The ones we need to convince are YOU – the chip and system-level designers – about the benefits of 3D ICs. Because until you design 3D in, nobody’s going to manufacture 3D ICs in high volume, no matter how ready we are.

We talk a lot about co-design and co-development as critical to 3D IC manufacturing. This also includes sharing of knowledge between the design community and the manufacturing community. This is the reason for my letter. I’d like to invite you to the 3D IC party as our guest of honor, because without you on board, this ship may never really sail. We’d like to see more of you participate in 3D IC events, and we’d be happy to send 3D ambassadors to present at yours. Let’s get the dialogue going.

Best Regards,

Françoise